
Reset
4-2
MPC801 USER’S MANUAL
MOTOROLA
4
External soft reset
Internal soft reset
— Debug port soft reset
All of these reset sources are fed into the reset controller and, depending on the source of
the reset, different actions are taken. The reset status register reflects the last source to
cause a reset.
4.1.1 Power-On Reset
Power-on reset is an active low input pin called PORESET. In a system with power-down
low-power mode, this pin should only be activated when a voltage in the keep alive power
(KAPWR) rail fails. When this pin is asserted, the MODCK bits are sampled and the
phase-locked loop multiplication factor and pitrtclk and tmbclk sources are changed to their
default values. When this pin is negated, internal MODCK values are unchanged. The
PORESET pin should be asserted for a minimum of 3
assertion, the MPC801 enters the power-on reset state and stays there until the following
events occur:
microseconds. After detecting this
The internal PLL enters the lock state and the system clock is active
The PORESET pin is negated
When PORESET is asserted, the MPC801 enters the power-on reset (POR) state in which
SRESET and HRESET are asserted by the core. When the MPC801 remains in POR, the
extension counter of 512 is reset,and the MODCK pins are sampled when POR pin is
negated. After the negation of PORESET or PLL lock, the core enters the state of internal
initiated HRESET and continues driving the HRESET and SRESET pins for 512 cycles.
When the timer expires, which is usually after the 512 cycles, the configuration is sampled
from the data pins and the core stops driving the pins. An external pull-up resistor should
drive the HRESET and SRESET pins high. After the pins are negated, a 16-cycle period
passes before the presence of an external (hard/soft) reset is tested. Refer to
Hard Reset
for more information.
Section 4.3.1
4.1.2 External Hard Reset
HRESET (hard reset) is a bidirectional, active low I/O pin. The MPC801 can only detect an
external assertion of HRESET if it occurs while the MPC801 is not asserting reset. During
HRESET, SRESET is asserted. HRESET is an open-collector type of pin. SRESET (soft
reset) is a bidirectional, active low I/O pin. The MPC801 can only detect an external
assertion of SRESET if it occurs while the MPC801 is not asserting reset. The SRESET is
also an open-collector type of pin.
When an external HRESET is asserted, the core starts driving the HRESET and SRESET
for 512 cycles. When the timer expires, after 512 cycles, the configuration is sampled from
the data pins and the core stops driving the HRESET and SRESET pins. An external pull-up
resistor should drive the pins high and once they are negated, a 16-cycle period passes
before the presence of an external (hard/soft) reset is tested. Refer to
Reset
for more information.
Section 4.3.1 Hard