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| 型號(hào)： | XIO2200AEVM |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 57/202頁(yè) |
| 文件大小： | 0K |
| 描述： | XIO2200AEVM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，PCI 至 PCI 橋 |
| 已用 IC / 零件： | XIO2200A |
| 次要屬性： | LED 狀態(tài)指示器 |
| 已供物品： | 模塊 |
| 相關(guān)產(chǎn)品： | 296-21636-ND - IC PCI-EXPRESS/BUS BRIDGE 175BGA 296-19617-ND - IC PCI-EXPRESS/BUS BRIDGE 176BGA 296-19567-ND - IC PCI-EXPRESS/BUS BRIDGE 176BGA 296-19486-ND - IC PCI-EXPRESS/BUS BRIDGE 176BGA 296-19485-ND - IC PCI-EXPRESS/BUS BRIDGE 176BGA |
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Introduction
2
March 5 2007 June 2011
SCPS154C
2
Introduction
The Texas Instruments XIO2200A is a single-function PCI Express to PCI local bus translation bridge where
the PCI bus interface is internally connected to a 1394a-2000 open host controller link-layer controller with
a two-port 1394a PHY. When the XIO2200A is properly configured, this solution provides full PCI Express and
1394a functionality and performance.
2.1
Description
The XIO2200A is a single-function PCI Express to PCI translation bridge where the PCI bus interface is
internally connected to a 1394a open host controller link-layer controller with a two-port 1394a PHY. The
PCI-Express to PCI translation bridge is fully compatible with the PCI Express to PCI/PCI-X Bridge
Specification, Revision 1.0. Also, the bridge supports the standard PCI-to-PCI bridge programming model.
The 1394a OHCI controller function is fully compatible with IEEE Standard 1394a-2000 and the latest 1394
Open Host Controller Interface (OHCI) Specification.
For downstream traffic, the PCI Express to PCI translation bridge simultaneously supports up to eight posted
and four nonposted transactions for each enabled virtual channel (VC). For upstream traffic, up to six posted
and four nonposted transactions are simultaneously supported for each VC.
The PCI Express interface supports a x1 link operating at full 250 MB/s packet throughput in each direction
simultaneously. Two independent VCs are supported. The second VC is optimized for isochronous traffic
types and quality-of-service (QoS) applications. Also, the bridge supports the advanced error reporting
capability including ECRC as defined in the PCI Express Base Specification, Revision 1.0a. Supplemental
firmware or software is required to fully utilize both of these features.
Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are
detected, then packet poisoning is supported for both upstream and downstream operations.
Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The bridge provides
physical write posting and a highly tuned physical data path for SBP-2 performance. The bridge is capable
of transferring data between the PCI Express bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M
bits/s. The bridge provides two 1394 ports that have separate cable bias (TPBIAS). The bridge also supports
the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration
enhancements.
As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a-2000, internal
control registers are memory-mapped and nonprefetchable. This configuration header is accessed through
configuration cycles specified by PCI Express, and it provides plug-and-play (PnP) compatibility.
The PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in
a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status, for initialization
and arbitration, and for packet reception and transmission. An external 2-wire serial EEPROM interface is
provided to load the global unique ID for the 1394 fabric.
Power management (PM) features include active state link PM, PME mechanisms, the beacon and wake
protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically
saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK
messages are supported.
Eight general-purpose inputs and outputs (GPIOs), configured through accesses to the PCI Express
configuration space, allow for further system control and customization.
Not Recommended for New Designs
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| XIO2200AGGW | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI Exp-PCI Bus Trans Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XIO2200AZGW | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI Exp-PCI Bus Trans Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XIO2200AZGW | 制造商:Texas Instruments 功能描述:PCI Express to PCI Bus Converter IC |
| XIO2200AZHH | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI Exp-PCI Bus Trans Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XIO2200GGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(pán)（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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