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參數(shù)資料
| 型號： | XE8000EV121 |
| 廠商： | Semtech |
| 文件頁數(shù)： | 9/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR SX8723/24 |
| 標準包裝： | 1 |
| 主要目的： | 接口，傳感器至模數(shù)轉換器接口，可編程 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | SX8723，SX8724，SX8725 |
| 主要屬性： | 用于橋型傳感器的信號調節(jié) |
| 次要屬性： | GUI，最多 16 位，1/12 ~ 1000 可編程增益，I2C 接口 |
| 已供物品： | 板，CD |
| 產(chǎn)品目錄頁面： | 585 (CN2011-ZH PDF) |
| 相關產(chǎn)品： | SX8725E083DKR-ND - IC DAS PRESSURE/TEMP SENS 12MLPD SX8724E082DKR-ND - IC DAS PRESSURE/TEMP SENS 16MLPQ SX8725E083CT-ND - IC DAS PRESSURE/TEMP SENS 12MLPD SX8724E082CT-ND - IC DAS PRESSURE/TEMP SENS 16MLPQ SX8725E083TR-ND - IC DAS PRESSURE/TEMP SENS 12MLPD SX8724E082TR-ND - IC DAS PRESSURE/TEMP SENS 16MLPQ |
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ADVANCED COMMUNICATIONS & SENSING
V1.23 2009 Semtech Corp.
www.semtech.com
17
SX8724
ZoomingADC for Pressure and Temperature Sensing
Registers
The system has a bank of eight 8-bit registers: six registers are used to configure the acquisition chain
(RegAcCfg0 to 5), and two registers are used to store the output code of the analog-to-digital conversion
(RegAcOutMsb & Lsb).
Bit Position
Register Name
7
6
5
4
3
2
1
0
RegACOutLsb
OUT[7:0]
RegACOutMsb
OUT[15:8]
RegACCfg0
Default values:
START
0
SET_NELC[1:0]
01
SET_OSR[2:0]
010
CONT
0
-
0
RegACCfg1
Default values:
IB_AMP_ADC[1:0]
11
IB_AMP_PGA[1:0]
11
ENABLE[3:0]
0000
RegACCfg2
Default values:
FIN[1:0]
00
PGA2_GAIN[1:0]
00
PGA2_OFFSET[3:0]
0000
RegACCfg3
Default values:
PGA1_G
0
PGA3_GAIN[6:0]
0001100
RegACCfg4
Default values:
-
0
PGA3_OFFSET[6:0]
0000000
RegACCfg5
Default values:
BUSY
0
DEF
0
AMUX[4:0]
00000
VMUX
0
Table 1 - Peripheral Registers to Configure the Acquisition Chain (AC)
and to Store the Analog-to-Digital Conversion (ADC) Result
With:
OUT: (r) digital output code of the analog-to-digital converter. (MSB = OUT[15])
START: (w) setting this bit triggers a single conversion (after the current one is finished). This bit always reads back 0.
SET_NELC: (rw) sets the number of elementary conversions to 2 SET_NELC[1:0]. To compensate for offsets, the input signal is
chopped between elementary conversions (1,2,4,8).
SET_OSR: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2(3+SET_OSR[2:0]). OSR = 8, 16, 32, ..., 512,
1024.
CONT: (rw) setting this bit starts a conversion. A new conversion will automatically begin as long as the bit remains at 1.
TEST: bit only used for test purposes. In normal mode, this bit is forced to 0 and cannot be overwritten.
IB_AMP_ADC: (rw) sets the bias current in the ADC to 0.25*(1+ IB_AMP_ADC[1:0]) of the normal operation current (25, 50, 75 or
100% of nominal current). To be used for low-power, low-speed operation.
IB_AMP_PGA: (rw) sets the bias current in the PGAs to 0.25*(1+IB_AMP_PGA[1:0]) of the normal operation current (25, 50, 75 or
100% of nominal current). To be used for low-power, low-speed operation.
ENABLE: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are
disabled are bypassed.
FIN: (rw) These bits set the over sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency,
the sampling frequency is given as: 11
500 kHz, 10
250 kHz, 01
125 kHz, 00
62.5 kHz.
PGA1_GAIN: (rw) sets the gain of the first stage: 0
1, 1
10.
PGA2_GAIN: (rw) sets the gain of the second stage: 00
1, 01
2, 10
5, 11
10.
PGA3_GAIN: (rw) sets the gain of the third stage to PGA3_GAIN[6:0]
1/12.
PGA2_OFFSET: (rw) sets the offset of the second stage between –1 and +1, with increments of 0.2. The MSB gives the sign
(0
→ positive, 1 → negative); amplitude is coded with the bits PGA2_OFFSET[5:0].
PGA3_OFFSET: (rw) sets the offset of the third stage between –5.25 and +5.25, with increments of 1/12. The MSB gives the sign
(0
→ positive, 1 → negative); amplitude is coded with the bits PGA3_OFFSET[5:0].
BUSY: (r) set to 1 if a conversion is running.
DEF: (w) sets all values to their defaults (PGA disabled, max speed, nominal modulator bias current, 2 elementary conversions,
over-sampling rate of 32) and starts a new conversion without waiting the end of the preceding one.
AMUX(4:0): (rw) AMUX(4) sets the mode (0
differential inputs, 1
single ended inputs with A0 = common reference) AMUX(3)
sets the sign (0
straight, 1
cross) AMUX(2:0) sets the channel.
VMUX: (rw) sets the differential reference channel (0
VBATT, 1
VREF).
(r = read; w = write; rw = read & write)
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