1. 收藏本站
      • 您好,
        買賣IC網(wǎng)歡迎您。
      • 請登錄
      • 免費(fèi)注冊
      • 我的買賣
      • 新采購0
      • VIP會員服務(wù)
      • [北京]010-87982920
      • [深圳]0755-82701186
      • 網(wǎng)站導(dǎo)航
      發(fā)布緊急采購
      • IC現(xiàn)貨
      • IC急購
      • 電子元器件
      VIP會員服務(wù)
      • 您現(xiàn)在的位置:買賣IC網(wǎng) > PDF目錄4214 > XCV405E-7FG676I (Xilinx Inc)IC FPGA 1.8V 676-BGA PDF資料下載
      參數(shù)資料
      型號: XCV405E-7FG676I
      廠商: Xilinx Inc
      文件頁數(shù): 49/118頁
      文件大?。?/td> 0K
      描述: IC FPGA 1.8V 676-BGA
      產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
      標(biāo)準(zhǔn)包裝: 1
      系列: Virtex®-E EM
      LAB/CLB數(shù): 2400
      邏輯元件/單元數(shù): 10800
      RAM 位總計(jì): 573440
      輸入/輸出數(shù): 404
      門數(shù): 129600
      電源電壓: 1.71 V ~ 1.89 V
      安裝類型: 表面貼裝
      工作溫度: -40°C ~ 100°C
      封裝/外殼: 676-BGA
      供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
      第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁當(dāng)前第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁
      Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
      Module 2 of 4
      www.xilinx.com
      DS025-2 (v3.0) March 21, 2014
      32
      R
      — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
      Fundamentals
      Modern bus applications, pioneered by the largest and most
      influential companies in the digital electronics industry, are
      commonly introduced with a new I/O standard tailored spe-
      cifically to the needs of that application. The bus I/O stan-
      dards provide specifications to other vendors who create
      products designed to interface with these applications.
      Each standard often has its own specifications for current,
      voltage, I/O buffering, and termination techniques.
      The ability to provide the flexibility and time-to-market
      advantages of programmable logic is increasingly depen-
      dent on the capability of the programmable logic device to
      support an ever increasing variety of I/O standards
      The SelectI/O resources feature highly configurable input
      and output buffers which provide support for a wide variety
      of I/O standards. As shown in Table 18, each buffer type can
      support a variety of voltage requirements.
      Overview of Supported I/O Standards
      This section provides a brief overview of the I/O standards
      supported by all Virtex-E devices.
      While most I/O standards specify a range of allowed volt-
      ages, this document records typical voltage values only.
      Detailed information on each specification can be found on
      the Electronic Industry Alliance Jedec website at:
      http://www.jedec.org
      LVTTL — Low-Voltage TTL
      The Low-Voltage TTL, or LVTTL standard is a general pur-
      pose EIA/JESDSA standard for 3.3 V applications that uses
      an LVTTL input buffer and a Push-Pull output buffer. This
      standard requires a 3.3 V output source voltage (VCCO), but
      does not require the use of a reference voltage (VREF) or a
      termination voltage (VTT).
      LVCMOS2 — Low-Voltage CMOS for 2.5 Volts
      The Low-Voltage CMOS for 2.5 Volts or lower, or LVCMOS2
      standard is an extension of the LVCMOS standard (JESD
      8.-5) used for general purpose 2.5 V applications. This stan-
      dard requires a 2.5 V output source voltage (VCCO), but
      does not require the use of a reference voltage (VREF) or a
      board termination voltage (VTT).
      LVCMOS18 — 1.8 V Low Voltage CMOS
      This standard is an extension of the LVCMOS standard. It is
      used in general purpose 1.8 V applications. The use of a
      reference voltage (VREF) or a board termination voltage
      (VTT) is not required.
      PCI — Peripheral Component Interface
      The Peripheral Component Interface, or PCI standard spec-
      ifies support for both 33 MHz and 66 MHz PCI bus applica-
      tions. It uses a LVTTL input buffer and a Push-Pull output
      buffer. This standard does not require the use of a reference
      voltage (VREF) or a board termination voltage (VTT), how-
      ever, it does require a 3.3 V output source voltage (VCCO).
      GTL — Gunning Transceiver Logic Terminated
      The Gunning Transceiver Logic, or GTL standard is a
      high-speed bus standard (JESD8.3) invented by Xerox.
      Xilinx has implemented the terminated variation for this
      standard. This standard requires a differential amplifier
      input buffer and a Open Drain output buffer.
      GTL+ — Gunning Transceiver Logic Plus
      The Gunning Transceiver Logic Plus, or GTL+ standard is a
      high-speed bus standard (JESD8.3) first used by the Pen-
      tium Pro processor.
      HSTL — High-Speed Transceiver Logic
      The High-Speed Transceiver Logic, or HSTL standard is a
      general purpose high-speed, 1.5 V bus standard sponsored
      by IBM (EIA/JESD 8-6). This standard has four variations or
      classes. SelectI/O devices support Class I, III, and IV. This
      Table 18:
      Virtex-E Supported I/O Standards
      I/O
      Standard
      Output
      VCCO
      Input
      VCCO
      Input
      VREF
      Board
      Termination
      Voltage (VTT)
      LVTTL
      3.3
      N/A
      LVCMOS2
      2.5
      N/A
      LVCMOS18
      1.8
      N/A
      SSTL3 I & II
      3.3
      N/A
      1.50
      SSTL2 I & II
      2.5
      N/A
      1.25
      GTL
      N/A
      0.80
      1.20
      GTL+
      N/A
      1.0
      1.50
      HSTL I
      1.5
      N/A
      0.75
      HSTL III & IV
      1.5
      N/A
      0.90
      1.50
      CTT
      3.3
      N/A
      1.50
      AGP-2X
      3.3
      N/A
      1.32
      N/A
      PCI33_3
      3.3
      N/A
      PCI66_3
      3.3
      N/A
      BLVDS & LVDS
      2.5
      N/A
      LVPECL
      3.3
      N/A
      相關(guān)PDF資料
      PDF描述
      XC6VLX195T-1FFG784C IC FPGA VIRTEX 6 199K 784FFGBGA
      XC6VCX130T-2FFG784I IC FPGA VIRTEX 6 128K 784FFGBGA
      XC4VLX60-11FF668I IC FPGA VIRTEX-4LX 668FFBGA
      XC4VLX60-12FFG668C IC FPGA VIRTEX-4 LX 60K 668FCBGA
      XC4VLX60-11FFG668I IC FPGA VIRTEX-4 LX 60K 668FCBGA
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      XCV405E-7FG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
      XCV405E-7FG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
      XCV405E-8BG404C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
      XCV405E-8BG404I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
      XCV405E-8BG556C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
      發(fā)布緊急采購,3分鐘左右您將得到回復(fù)。

      采購需求

      (若只采購一條型號,填寫一行即可)

      發(fā)布成功!您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺,查看報(bào)價(jià)

      發(fā)布成功!您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺,查看報(bào)價(jià)

      *型號 *數(shù)量 廠商 批號 封裝
      添加更多采購

      我的聯(lián)系方式

      *
      *
      *
      • VIP會員服務(wù) |
      • 廣告服務(wù) |
      • 付款方式 |
      • 聯(lián)系我們 |
      • 招聘銷售 |
      • 免責(zé)條款 |
      • 網(wǎng)站地圖

      感谢您访问我们的网站,您可能还对以下资源感兴趣:

      三级特黄60分钟在线观看,美女在线永久免费网站,边吃奶边摸下很爽视频,娇妻在厨房被朋友玩得呻吟`

    2. <big id="s6sjg"><label id="s6sjg"><li id="s6sjg"></li></label></big>
      <samp id="s6sjg"><strong id="s6sjg"><u id="s6sjg"></u></strong></samp>

    3. <big id="s6sjg"></big>