參數(shù)資料
型號: XCV405E-7FG676C
廠商: Xilinx Inc
文件頁數(shù): 88/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 676-FBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 2400
邏輯元件/單元數(shù): 10800
RAM 位總計: 573440
輸入/輸出數(shù): 404
門數(shù): 129600
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v3.0) March 21, 2014
Module 3 of 4
15
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Block RAM Switching Characteristics
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Description(1)
Symbol
Speed Grade
Units
Min
-8
-7
-6
Sequential Delays
Clock CLK to DOUT output
TBCKO
0.63
2.46
3.1
3.5
ns, max
Setup and Hold Times before Clock CLK
ADDR inputs
TBACK/TBCKA
0.42 / 0
0.9 / 0
1.0 / 0
1.1 / 0
ns, min
DIN inputs
TBDCK/TBCKD
0.42 / 0
0.9 / 0
1.0 / 0
1.1 / 0
ns, min
EN input
TBECK/TBCKE
0.97 / 0
2.0 / 0
2.2 / 0
2.5 / 0
ns, min
RST input
TBRCK/TBCKR
0.9 / 0
1.8 / 0
2.1 / 0
2.3 / 0
ns, min
WEN input
TBWCK/TBCKW
0.86 / 0
1.7 / 0
2.0 / 0
2.2 / 0
ns, min
Clock CLK
Minimum Pulse Width, High
TBPWH
0.6
1.2
1.35
1.5
ns, min
Minimum Pulse Width, Low
TBPWL
0.6
1.2
1.35
1.5
ns, min
CLKA -> CLKB setup time for different ports
TBCCS
1.2
2.4
2.7
3.0
ns, min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
Description
Symbol
Speed Grade
Units
Min
-8
-7
-6
Combinatorial Delays
IN input to OUT output
TIO
0.0
0 .0
ns, max
TRI input to OUT output high-impedance
TOFF
0.05
0.092
0.10
0.11
ns, max
TRI input to valid data on OUT output
TON
0.05
0.092
0.10
0.11
ns, max
Description
Symbol
Value
Units
TMS and TDI Setup times before TCK
TTAPTK
4.0
ns, min
TMS and TDI Hold times after TCK
TTCKTAP
2.0
ns, min
Output delay from clock TCK to output TDO
TTCKTDO
11.0
ns, max
Maximum TCK clock frequency
FTCK
33
MHz, max
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XCV405E-7FG676I 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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