- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375018 > XCV300E-6TQ144C (Xilinx, Inc.) Field Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號(hào)： | XCV300E-6TQ144C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大小： | 87K |
| 代理商： | XCV300E-6TQ144C |
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
Module 1 of 4
1
Features
Fast, High-Density 1.8 V FPGA Family
-
Densities from 58 k to 4 M system gates
-
130 MHz internal performance (four LUT levels)
-
Designed for low-power operation
-
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
Highly Flexible SelectI/O+ Technology
-
Supports 20 high-performance interface standards
-
Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/s
Differential Signalling Support
-
LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
-
Differential I/O signals can be input, output, or I/O
-
Compatible with standard differential devices
-
LVPECL and LVDS clock inputs for 300+ MHz
clocks
Proprietary High-Performance SelectLink
Technology
-
Double Data Rate (DDR) to Virtex-E link
-
Web-based HDL generation methodology
Sophisticated SelectRAM+ Memory Hierarchy
-
1 Mb of internal configurable distributed RAM
-
Up to 832 Kb of synchronous internal block RAM
-
True Dual-Port BlockRAM capability
-
Memory bandwidth up to 1.66 Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)
-
Designed for high-performance Interfaces to
External Memories
-
200 MHz ZBT* SRAMs
-
200 Mb/s DDR SDRAMs
-
Supported by free Synthesizable reference design
High-Performance Built-In Clock Management Circuitry
-
Eight fully digital Delay-Locked Loops (DLLs)
-
Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications
-
Clock Multiply and Divide
-
Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
Flexible Architecture Balances Speed and Density
-
Dedicated carry logic for high-speed arithmetic
-
Dedicated multiplier support
-
Cascade chain for wide-input function
-
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
-
Internal 3-state bussing
-
IEEE 1149.1 boundary-scan logic
-
Die-temperature sensor diode
Supported by Xilinx Foundation and Alliance Series
Development Systems
-
Further compile time reduction of 50%
-
Internet Team Design (ITD) tool ideal for
million-plus gate density designs
-
Wide selection of PC and workstation platforms
SRAM-Based In-System Configuration
-
Unlimited re-programmability
Advanced Packaging Options
-
0.8 mm Chip-scale
-
1.0 mm BGA
-
1.27 mm BGA
-
HQ/PQ
0.18
m
m 6-Layer Metal Process
100% Factory Tested
* ZBT is a trademark of Integrated Device Technology, Inc.
0
Virtex-E 1.8 V
Field Programmable Gate Arrays
DS022-1 (v2.2) November 9, 2001
0
0
Preliminary Product Specification
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV300E-6TQ144I | Field Programmable Gate Arrays |
| XCV300E-7BG352C | Field Programmable Gate Arrays |
| XCV300E-7BG352I | Field Programmable Gate Arrays |
| XCV300E-7CS144C | TAPE, SEMICOND, RUBBER, 19MMX4.5M; Length, Reel (Metric):45m; Length, tape:45m; Material:Ethylene Propylene Rubber; Width, tape:19mm RoHS Compliant: NA |
| XCV300E-7CS144I | TAPE, CORONA, CHEMRES, 25MMX9.15M; Length, Reel (Metric):9.15m; Width, external:25mm RoHS Compliant: NA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV300E-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV300E-7BG204C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virte -E 1.8 V Field Programmable Gate Arrays |
| XCV300E-7BG204I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virte -E 1.8 V Field Programmable Gate Arrays |
| XCV300E-7BG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV300E-7BG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。