參數(shù)資料
型號(hào)： XCS40XL-4PQG208C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 50/83頁(yè)
文件大?。?/td> 0K
描述： IC SPARTAN-XL FPGA 40K 208-PQFP
產(chǎn)品變化通告： Product Discontinuation 26/Oct/2011
標(biāo)準(zhǔn)包裝： 24
系列： Spartan®-XL
LAB/CLB數(shù)： 784
邏輯元件/單元數(shù)： 1862
RAM 位總計(jì)： 25088
輸入/輸出數(shù)： 169
門數(shù)： 40000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
其它名稱： 122-1300
Spartan and Spartan-XL FPGA Families Data Sheet
54
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family Global Buffer Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
terns. Listed below are representative values where one
global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB
flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Symbol
Description
Device
Speed Grade
Units
-5
-4
Max
TGLS
From pad through buffer, to any clock K
XCS05XL
1.4
1.5
ns
XCS10XL
1.7
1.8
ns
XCS20XL
2.0
2.1
ns
XCS30XL
2.3
2.5
ns
XCS40XL
2.6
2.8
ns
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