參數資料
| 型號： | XCS30-3BG256C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 61/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 5V C-TEMP 256-PBGA |
| 標準包裝： | 40 |
| 系列： | Spartan® |
| LAB/CLB數： | 576 |
| 邏輯元件/單元數： | 1368 |
| RAM 位總計： | 18432 |
| 輸入/輸出數： | 192 |
| 門數： | 30000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 256-BBGA |
| 供應商設備封裝： | 256-PBGA |
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Spartan and Spartan-XL FPGA Families Data Sheet
64
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
SGCK1 -
SGCK4
(Spartan)
Weak
Pull-up
(except
SGCK4
is DOUT)
I or I/O
Four Secondary Global inputs each drive a dedicated internal global net with short
delay and minimal skew. These internal global nets can also be driven from
internal logic. If not used to drive a global net, any of these pins is a
user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global
Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol
is automatically placed on one of these pins.
GCK1 -
GCK8
(Spartan-XL)
Weak
Pull-up
(except
GCK6 is
DOUT)
I or I/O
Eight Global inputs each drive a dedicated internal global net with short delay and
minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew
Buffers. Any input pad symbol connected directly to the input of a BUFGLS symbol
is automatically placed on one of these pins.
CS1
(Spartan-XL)
I
I/O
During Express configuration, CS1 is used as a serial-enable signal for
daisy-chaining.
D0-D7
(Spartan-XL)
I
I/O
During Express configuration, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.
DIN
I
I/O
During Slave Serial or Master Serial configuration, DIN is the serial configuration
data input receiving data on the rising edge of CCLK. After configuration, DIN is a
user-programmable I/O pin.
DOUT
O
I/O
During Slave Serial or Master Serial configuration, DOUT is the serial
configuration data output that can drive the DIN of daisy-chained slave FPGAs.
DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods
after it was received at the DIN input.
In Spartan-XL family Express mode, DOUT is the status output that can drive the
CS1 of daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O Pins
I/O
Weak
Pull-up
I/O
These pins can be configured to be input and/or output after configuration is
completed. Before configuration is completed, these pins have an internal
high-value pull-up resistor network that defines the logic level as High.
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O After
Config.
Pin Description
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XCS30-3BG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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