參數(shù)資料
型號(hào)： XCS10XL-5PC84C
廠商： Xilinx Inc
文件頁(yè)數(shù)： 78/83頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 3.3V C-TEMP 84-PLCC
標(biāo)準(zhǔn)包裝： 15
系列： Spartan®-XL
LAB/CLB數(shù)： 196
邏輯元件/單元數(shù)： 466
RAM 位總計(jì)： 6272
輸入/輸出數(shù)： 61
門(mén)數(shù)： 10000
電源電壓： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
Spartan and Spartan-XL FPGA Families Data Sheet
8
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan-XL Family VCC Clamping
Spartan-XL FPGAs have an optional clamping diode con-
nected from each I/O to VCC. When enabled they clamp
ringing transients back to the 3.3V supply rail. This clamping
action is required in 3.3V PCI applications. VCC clamping is
a global option affecting all I/O pins.
Spartan-XL devices are fully 5V TTL I/O compatible if VCC
clamping is not enabled. With VCC clamping enabled, the
Spartan-XL devices will begin to clamp input voltages to
one diode voltage drop above VCC. If enabled, TTL I/O com-
patibility is maintained but full 5V I/O tolerance is sacrificed.
The user may select either 5V tolerance (default) or 3.3V
PCI compatibility. In both cases negative voltage is clamped
to one diode voltage drop below ground.
Spartan-XL devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in Table 5.
Additional Fast Capture Input Latch (Spartan-XL Family
Only)
The Spartan-XL family OB has an additional optional latch
on the input. This latch is clocked by the clock used for the
output flip-flop rather than the input clock. Therefore, two
different clocks can be used to clock the two input storage
elements. This additional latch allows the fast capture of
input data, which is then synchronized to the internal clock
by the IOB flip-flop or latch.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active High
input flip-flop. ILFLX is a transparent Low Fast Capture latch
followed by a transparent High input latch. Any of the clock
inputs can be inverted before driving the library element,
and the inverter is absorbed into the IOB.
IOB Output Signal Path
Output signals can be optionally inverted within the IOB,
and can pass directly to the output buffer or be stored in an
edge-triggered flip-flop and then to the output buffer. The
functionality of this flip-flop is shown in Table 6.
Table 4: Supported Sources for Spartan/XL Inputs
Source
Spartan
Inputs
Spartan-XL
Inputs
5V,
TTL
5V,
CMOS
3.3V
CMOS
Any device, VCC = 3.3V,
CMOS outputs
√
Unreli-
able
Data
√
Spartan family, VCC = 5V,
TTL outputs
√√
Any device, VCC = 5V,
TTL outputs (VOH ≤ 3.7V)
√√
Any device, VCC = 5V,
CMOS outputs
√√
√ (default
mode)
Table 5: I/O Standards Supported by Spartan-XL FPGAs
Signaling
Standard
VCC
Clamping
Output
Drive
VIH MAX
VIH MIN
VIL MAX
VOH MIN
VOL MAX
TTL
Not allowed
12/24 mA
5.5
2.0
0.8
2.4
0.4
LVTTL
OK
12/24 mA
3.6
2.0
0.8
2.4
0.4
PCI5V
Not allowed
24 mA
5.5
2.0
0.8
2.4
0.4
PCI3V
Required
12 mA
3.6
50% of VCC
30% of VCC
90% of VCC
10% of VCC
LVCMOS 3V
OK
12/24 mA
3.6
50% of VCC
30% of VCC
90% of VCC
10% of VCC
Table 6: Output Flip-Flop Functionality
Mode
Clock
Enable
T
D
Q
Power-Up
or GSR
XX
0*
X
SR
Flip-Flop
X
0
0*
X
Q
1*
0*
D
XX
1
X
Z
0X
0*
X
Q
Legend:
X
Don’t care
Rising edge (clock not inverted).
SR
Set or Reset value. Reset is default.
0*
Input is Low or unconnected (default value)
1*
Input is High or unconnected (default value)
Z
3-state
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