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參數(shù)資料
| 型號： | XCS10-4TQ144C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 25/83頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V C-TEMP 144-TQFP |
| 產(chǎn)品變化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 標準包裝： | 60 |
| 系列： | Spartan® |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 466 |
| RAM 位總計： | 6272 |
| 輸入/輸出數(shù)： | 112 |
| 門數(shù)： | 10000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
31
Product Specification
R
Product Obsolete/Under Obsolescence
Setting CCLK Frequency
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency ranges
from 0.5 MHz to 1.25 MHz for Spartan/XL devices. In fast
CCLK mode, the frequency ranges from 4 MHz to 10 MHz
for Spartan/XL devices. The frequency is changed to fast by
an option when running the bitstream generation software.
Data Stream Format
The data stream ("bitstream") format is identical for both
serial configuration modes, but different for the Spartan-XL
family Express mode. In Express mode, the device
becomes active when DONE goes High, therefore no length
count is required. Additionally, CRC error checking is not
supported in Express mode. The data stream format is
shown in Table 16. Bit-serial data is read from left to right.
Express mode data is shown with D0 at the left and D7 at
the right.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Spartan-XL
family Express mode). This header is followed by the actual
configuration data in frames. The length and number of
frames depends on the device type (see Table 17).
Each
frame begins with a start field and ends with an error check.
In serial modes, a postamble code is required to signal the
end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long daisy
chains require additional startup bytes to shift the last data
through the chain. All start-up bytes are "don’t cares".
Figure 28: Express Mode Programming Switching Characteristics
DS060_28_080400
BYTE
0
CCLK
FPGA Filled
INIT
TDC
TCD
TIC
D0-D7
DOUT
BYTE
1
BYTE
6
Header Received
Symbol
Description
Min
Max
Units
TIC
CCLK
INIT (High) setup time
5
-
μs
TDC
D0-D7 setup time
20
-
ns
TCD
D0-D7 hold time
0
-
ns
TCCH
CCLK High time
45
-
ns
TCCL
CCLK Low time
45
-
ns
FCC
CCLK Frequency
-
10
MHz
Notes:
1.
If not driven by the preceding DOUT, CS1 must remain High until the
device is fully configured.
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