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    參數(shù)資料
    

    


    


    
型號(hào)：
XCS10-3VQ100C

    

    
廠商：
Xilinx Inc

    

    
文件頁(yè)數(shù)：
29/83頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA 5V C-TEMP 100-VQFP

    

    
產(chǎn)品變化通告：
Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 
    		

    

    
標(biāo)準(zhǔn)包裝：
90

    

    
系列：
Spartan®

    

    
LAB/CLB數(shù)：
196
    		

    

    
邏輯元件/單元數(shù)：
466
    		

    

    
RAM 位總計(jì)：
6272
    		

    

    
輸入/輸出數(shù)：
77
    		

    

    
門數(shù)：
10000
    		

    

    
電源電壓：
4.75 V ~ 5.25 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
100-TQFP
    		

    

    
供應(yīng)商設(shè)備封裝：
100-VQFP（14x14）
    		

    

    

    

	
    
    
    

    
    
	
    Spartan and Spartan-XL FPGA Families Data Sheet
    DS060 (v2.0) March 1, 2013
    35
    Product Specification
    R
    Product Obsolete/Under Obsolescence
    Configuration
    The 0010 preamble code indicates that the following 24 bits
    represent the length count for serial modes. The length
    count is the total number of configuration clocks needed to
    load the complete configuration data. (Four additional con-
    figuration clocks are required to complete the configuration
    process, as discussed below.) After the preamble and the
    length count have been passed through to any device in the
    daisy chain, its DOUT is held High to prevent frame start
    bits from reaching any daisy-chained devices. In Spar-
    tan-XL family Express mode, the length count bits are
    ignored, and DOUT is held Low, to disable the next device in
    the pseudo daisy chain.
    A specific configuration bit, early in the first frame of a mas-
    ter device, controls the configuration-clock rate and can
    increase it by a factor of eight. Therefore, if a fast configura-
    tion clock is selected by the bitstream, the slower clock rate
    is used until this configuration bit is detected.
    Each frame has a start field followed by the frame-configu-
    ration data bits and a frame error field. If a frame data error
    is detected, the FPGA halts loading, and signals the error by
    pulling the open-drain INIT pin Low. After all configuration
    frames have been loaded into an FPGA using a serial
    mode, DOUT again follows the input data so that the
    remaining data is passed on to the next device. In
    Spartan-XL family Express mode, when the first device is
    fully programmed, DOUT goes High to enable the next
    device in the chain.
    Delaying Configuration After Power-Up
    There are two methods of delaying configuration after
    power-up: put a logic Low on the PROGRAM input, or pull
    the bidirectional INIT pin Low, using an open-collector
    (open-drain) driver. (See Figure 30.)
    A Low on the PROGRAM input is the more radical
    approach, and is recommended when the power-supply rise
    time is excessive or poorly defined. As long as PROGRAM
    is Low, the FPGA keeps clearing its configuration memory.
    When PROGRAM goes High, the configuration memory is
    cleared one more time, followed by the beginning of config-
    uration, provided the INIT input is not externally held Low.
    Note that a Low on the PROGRAM input automatically
    forces a Low on the INIT output. The Spartan/XL FPGA
    PROGRAM pin has a permanent weak pull-up.
    Avoid holding PROGRAM Low for more than 500
    μs. The
    500
    μs maximum limit is only a recommendation, not a
    requirement. The only effect of holding PROGRAM Low for
    more than 500
    μs is an increase in current, measured at
    about 40 mA in the XCS40XL. This increased current can-
    not damage the device. This applies only during reconfigu-
    ration, not during power-up. The INIT pin can also be held
    Low to delay reconfiguration, and the same characteristics
    apply as for the PROGRAM pin.
    Using an open-collector or open-drain driver to hold INIT
    Low before the beginning of configuration causes the FPGA
    Figure 30: Power-up Configuration Sequence
    INIT
    High? if
    Master
    Sample
    Mode Line
    Load One
    Configuration
    Data Frame
    Frame
    Error
    Pass
    Configuration
    Data to DOUT
    VCC
    Valid
    No
    Yes
    No
    Yes
    Operational
    Start-Up
    Sequence
    No
    Yes
    ~1.3
    μs per Frame
    Master Delays Before
    Sampling Mode Line
    Master CCLK
    Goes Active
    F
    Pull INIT Low
    and Stop
    DS060_30_080400
    EXTEST*
    SAMPLE/PRELOAD
    BYPASS
    CONFIGURE*
    (* if PROGRAM = High)
    SAMPLE/PRELOAD
    BYPASS
    EXTEST
    SAMPLE PRELOAD
    BYPASS
    USER 1
    USER 2
    CONFIGURE
    READBACK
    If Boundary Scan
    is Selected
    Config-
    uration
    memory
    Full
    CCLK
    Count Equals
    Length
    Count
    Completely Clear
    Configuration Memory
    Once More
    LDC
    Output
    =
    L,
    HDC
    Output
    =
    H
    Boundary Scan
    Instructions
    Available:
    I/O
    Active
    Keep Clearing
    Configuration
    Memory
    Test MODE, Generate
    One Time-Out Pulse
    of 16 or 64 ms
    PROGRAM
    = Low
    No
    Yes
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
XCS10-3TQ144C
IC FPGA 5V C-TEMP 144-TQFP

    

    
XCS10-3PC84C
IC FPGA 5V C-TEMP 84-PLCC

    

    
XCS05XL-5VQ100C
IC FPGA 3.3V C-TEMP 100-VQFP

    

    
XCS05XL-5PC84C
IC FPGA 3.3V C-TEMP 84-PLCC

    

    
65801-032LF
CLINCHER RECEPTACLE ASSY TIN

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XCS10-3VQ100I
功能描述:IC FPGA 5V I-TEMP 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

    

    
XCS10-3VQ144C
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS10-3VQ144I
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS10-3VQ208C
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS10-3VQ208I
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
    
    
    
	
    	
    
    
     
     
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