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參數(shù)資料
| 型號： | XCS05XL-5PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 14/83頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 84-PLCC |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計(jì)： | 3200 |
| 輸入/輸出數(shù)： | 61 |
| 門數(shù)： | 5000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
21
Product Specification
R
Product Obsolete/Under Obsolescence
Figure 20 is a diagram of the Spartan/XL FPGA boundary
scan logic. It includes three bits of Data Register per IOB,
the IEEE 1149.1 Test Access Port controller, and the
Instruction Register with decodes.
Spartan/XL devices can also be configured through the
boundary scan logic. See Configuration Through the
Data Registers
The primary data register is the boundary scan register. For
each IOB pin in the FPGA, bonded or not, it includes three
bits for In, Out and 3-state Control. Non-IOB pins have
appropriate partial bit population for In or Out only. PRO-
GRAM, CCLK and DONE are not included in the boundary
scan register. Each EXTEST CAPTURE-DR state captures
all In, Out, and 3-state pins.
The data register also includes the following non-pin bits:
TDO.T, and TDO.O, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD, which is
always the last bit of the data register. These three bound-
ary scan bits are special-purpose Xilinx test signals.
The other standard data register is the single flip-flop
BYPASS register. It synchronizes data being passed
through the FPGA to the next downstream boundary scan
device.
The FPGA provides two additional data registers that can
be specified using the BSCAN macro. The FPGA provides
two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are
the decodes of two user instructions. For these instructions,
two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2)
allow user scan data to be shifted out on TDO. The data
register clock (BSCAN.DRCK) is available for control of test
logic which the user may wish to implement with CLBs. The
NAND of TCK and RUN-TEST-IDLE is also provided
(BSCAN.IDLE).
Instruction Set
The Spartan/XL FPGA boundary scan instruction set also
includes instructions to configure the device and read back
the configuration data. The instruction set is coded as
shown in Table 12.
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