參數(shù)資料
型號(hào)： XCS05XL-4PC84C
廠商： Xilinx Inc
文件頁數(shù)： 39/83頁
文件大小： 0K
描述： IC FPGA 3.3V C-TEMP 84-PLCC
標(biāo)準(zhǔn)包裝： 15
系列： Spartan®-XL
LAB/CLB數(shù)： 100
邏輯元件/單元數(shù)： 238
RAM 位總計(jì)： 3200
輸入/輸出數(shù)： 61
門數(shù)： 5000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
Spartan and Spartan-XL FPGA Families Data Sheet
44
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
expressed in nanoseconds unless otherwise noted.
Symbol
Description
Speed Grade
Units
-4
-3
Min
Max
Min
Max
Clocks
TCH
Clock High time
3.0
-
4.0
-
ns
TCL
Clock Low time
3.0
-
4.0
-
ns
Combinatorial Delays
TILO
F/G inputs to X/Y outputs
-
1.2
-
1.6
ns
TIHO
F/G inputs via H to X/Y outputs
-
2.0
-
2.7
ns
THH1O
C inputs via H1 via H to X/Y outputs
-
1.7
-
2.2
ns
CLB Fast Carry Logic
TOPCY
Operand inputs (F1, F2, G1, G4) to COUT
-1.7
-2.1
ns
TASCY
Add/Subtract input (F3) to COUT
-2.8
-3.7
ns
TINCY
Initialization inputs (F1, F3) to COUT
-1.2
-1.4
ns
TSUM
CIN through function generators to X/Y outputs
-
2.0
-
2.6
ns
TBYP
CIN to COUT, bypass function generators
-
0.5
-
0.6
ns
Sequential Delays
TCKO
Clock K to Flip-Flop outputs Q
-
2.1
-
2.8
ns
Setup Time before Clock K
TICK
F/G inputs
1.8
-
2.4
-
ns
TIHCK
F/G inputs via H
2.9
-
3.9
-
ns
THH1CK
C inputs via H1 through H
2.3
-
3.3
-
ns
TDICK
C inputs via DIN
1.3
-
2.0
-
ns
TECCK
C inputs via EC
2.0
-
2.6
-
ns
TRCK
C inputs via S/R, going Low (inactive)
2.5
-
4.0
-
ns
Hold Time after Clock K
All Hold times, all devices
0.0
-
0.0
-
ns
Set/Reset Direct
TRPW
Width (High)
3.0
-
4.0
-
ns
TRIO
Delay from C inputs via S/R, going High to Q
-
3.0
-
4.0
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
11.5
-
13.5
-
ns
TMRQ
Delay from GSR input to any Q
See page 50 for TRRI values per device.
FTOG
Toggle Frequency (MHz)
(for export control purposes)
-
166
-
125
MHz
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