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參數(shù)資料
| 型號(hào)： | XCR3256XL-12PQ280I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 256 Macrocell CPLD |
| 中文描述： | 256個(gè)宏單元CPLD |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | XCR3256XL-12PQ280I |
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
1-800-255-77781
2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
. All other trademarks and registered trademarks are the property of their respective owners.
All specifications are subject to change without notice.
Features
7.5 ns pin-to-pin logic delays
System frequencies up to 140 MHz
256 macrocells with 6,000 usable gates
Available in small footprint packages
-
144-pin TQFP (116 user I/O pins)
-
208-pin PQFP (160 user I/O)
-
280-ball CS BGA (160 user I/O)
Optimized for 3.3V systems
-
Ultra low power operation
-
5V tolerant I/O pins with 3.3V core supply
-
Advanced 0.35 micron five metal layer re-
programmable process
-
FZP CMOS design technology
Advanced system features
-
In-system programming
-
Input registers
-
Predictable timing model
-
Up to 23 clocks available per logic block
-
Excellent pin retention during design changes
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
-
Four global clocks
-
Eight product term control terms per logic block
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V industrial grade voltage range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
Description
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 16 logic blocks provide
6,000 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 140 MHz.
TotalCMOS Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate
implementation allows Xilinx to offer CPLDs that are both
high performance and low power, breaking the paradigm
that to have low power, you must have low performance.
Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Fre-
quency of our XCR3256XL TotalCMOS CPLD (data taken
with 16 up/down, loadable 16-bit counters at 3.3V, 25
°
C).
0
XCR3256XL 256 Macrocell CPLD
DS013 (v1.2) May 3, 2000
0
14
Preliminary Product Specification
R
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| XCR3256XL-7PQ256C | 256 Macrocell CPLD |
| XCR3256XL-7PQ256I | 256 Macrocell CPLD |
| XCR3256XL-7PQ280C | 256 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3256XL-12PQG208C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 6K GATES 256 MCRCLLS 100MHZ COMM 0.35U - Trays |
| XCR3256XL-12PQG208I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 6K GATES 256 MCRCLLS 100MHZ IND 0.35UM - Trays |
| XCR3256XL-12TQ144C | 功能描述:IC CR CPLD 6K 256MCELL 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:90 系列:ispMACH® 4A 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.5ns 電壓電源 - 內(nèi)部:4.75 V ~ 5.25 V 邏輯元件/邏輯塊數(shù)目:- 宏單元數(shù):64 門(mén)數(shù):- 輸入/輸出數(shù):48 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤(pán) |
| XCR3256XL-12TQ144I | 制造商:Xilinx 功能描述:XLXXCR3256XL-12TQ144I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 6K GATES 256 MCRCLLS 100MHZ 0.35UM 3.3 - Trays |
| XCR3256XL-12TQ144Q | 制造商:Xilinx 功能描述:XILINX XCR3256XL-12TQ144Q CPLD - Trays 制造商:Xilinx 功能描述:Xilinx XCR3256XL-12TQ144Q CPLD |
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