參數(shù)資料
型號： XCR3128A-12TQ128I
廠商： Xilinx, Inc.
英文描述： CPLD with Enhanced Clocking
中文描述： CPLD的增強(qiáng)型時鐘
文件頁數(shù)： 8/17頁
文件大?。?/td> 268K
代理商： XCR3128A-12TQ128I
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DS035 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
8
3.3V, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
Design
-
Faster time-to-market
-
Debug partitioning and simplified prototyping
-
Printed circuit board reconfiguration during debug
-
Better device and board level testing
Manufacturing
-
Multi-functional hardware
-
Reconfigurability for test
-
Eliminates handling of "fine lead-pitch" components
for programming
-
Reduced inventory and manufacturing costs
-
Field Support
-
Easy remote upgrades and repair
-
Support for field configuration, reconfiguration, and
customization
Improved quality and reliability
The Xilinx XCR3128A allows for 3.3V in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally provided supervoltages, so that the XCR3128A
may be easily programmed on the circuit board using only
the 3V supply required by the device for normal operation.
A set of low-level ISP basic commands implemented in the
XCR3128A enable this feature. The ISP commands imple-
mented in the Xilinx XCR3128A are specified in
.
ISP commands
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