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參數資料
| 型號： | XCR3064XL-10CP56I |
| 廠商： | Xilinx Inc |
| 文件頁數： | 4/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ISP CPLD 64 MCELL 3.3V 56-CSP |
| 標準包裝： | 360 |
| 系列： | CoolRunner XPLA3 |
| 可編程類型： | 系統(tǒng)內可編程（最少 1K 次編程/擦除循環(huán)） |
| 最大延遲時間 tpd(1)： | 9.1ns |
| 電壓電源 - 內部： | 2.7 V ~ 3.6 V |
| 邏輯元件/邏輯塊數目： | 4 |
| 宏單元數： | 64 |
| 門數： | 1500 |
| 輸入/輸出數： | 48 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-LFBGA，CSPBGA |
| 供應商設備封裝： | 56-CSBGA（6x6） |
| 包裝： | 托盤 |
CoolRunner XPLA3 CPLD
12
DS012 (v2.5) May 26, 2009
Product Specification
R
Revision History
The following table shows the revision history for this document.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Date
Version
Revision
02/20/00
1.0
Initial Xilinx release.
03/06/00
1.1
Minor updates.
11/30/00
1.2
Updated Macrocell numbering, I/O pins, and available packages.
02/09/01
1.3
Updated specification.
04/11/01
1.4
Under Features, changed Global 3-state to Universal 3-state. Added XCR3512XL device;
changed TSU numbers, added 324-pin Fineline BGA package, Programming Specs:
changed TINIT from 50 min. to 50 max., Quality & Rel. specs: added NPE for UMC
devices—10,000 cycles.
01/07/02
1.5
package types, updated I/O cell section. Absolute Maximum Ratings table: Changed max
supply voltage relative to GND to 4.0V to match XC9500XL and UMC standard specs.
01/06/03
1.6
Changed from Advance Information to Preliminary. Added Note 1 to Figure 2 regarding
XCR3384XL TQ144 JTAG pins.
06/23/03
1.7
Added Power-Up Characteristics.
02/13/04
1.8
Added Maximum Soldering temperature (TSOL) specification. Added links.
09/29/04
1.9
Added text on shadow memory to first paragraph, page 2.
01/10/05
2.0
Changed Function Block input references to 40.
04/08/05
2.1
Add ICCSB Typical Specification
03/31/06
2.2
Added Warranty Disclaimer.
08/31/07
2.3
Added description of subthreshold power-up characteristics, page 6. Changes to Figure 7
and Table 3 on page 6 to describe subthreshold behavior. Add security description, page 6.
09/08/08
2.4
Removed PC44 and PCG44 packages. See Product Discontinuation Notice xcn07022.pdf.
05/26/09
2.5
Added note 3 to Table 2.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XCR3064XL-10CPG56C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 1.5K GATES 64 MCRCLLS 125MHZ 0.35UM 3. - Trays 制造商:Xilinx 功能描述:XLXXCR3064XL-10CPG56C IC SYSTEM GATE |
| XCR3064XL-10CPG56I | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 1.5K GATES 64 MCRCLLS 125MHZ 0.35UM 3. - Trays |
| XCR3064XL-10CS48C | 功能描述:IC ISP CPLD 64 MCELL 3.3V 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:CoolRunner XPLA3 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數目:24 宏單元數:384 門數:9000 輸入/輸出數:173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XCR3064XL-10CS48I | 功能描述:IC ISP CPLD 64 MCELL 3.3V 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:CoolRunner XPLA3 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數目:24 宏單元數:384 門數:9000 輸入/輸出數:173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XCR3064XL-10CSG48C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 1.5K GATES 64 MCRCLLS 125MHZ 0.35UM 3. - Trays 制造商:Xilinx 功能描述:XLXXCR3064XL-10CSG48C IC SYSTEM GATE |
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