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參數(shù)資料
| 型號： | XCF32PVG |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Platform Flash In-System Programmable Configuration PROMS |
| 中文描述： | 平臺Flash在系統(tǒng)可編程配置方案管理系統(tǒng) |
| 文件頁數(shù)： | 10/46頁 |
| 文件大小： | 525K |
| 代理商： | XCF32PVG |
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Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
10
R
PROM to FPGA Configuration Mode and Connections Summary
The FPGA's I/O, logical functions, and internal
interconnections are established by the configuration data
contained in the FPGA’s bitstream. The bitstream is loaded
into the FPGA either automatically upon power up, or on
command, depending on the state of the FPGA's mode
pins. Xilinx Platform Flash PROMs are designed to
download directly to the FPGA configuration interface.
FPGA configuration modes which are supported by the
XCFxxS Platform Flash PROMs include: Master Serial and
Slave Serial. FPGA configuration modes which are
supported by the XCFxxP Platform Flash PROMs include:
Master Serial, Slave Serial, Master SelectMAP, and Slave
SelectMAP. Below is a short summary of the supported
FPGA configuration modes. See the respective FPGA data
sheet for device configuration details, including which
configuration modes are supported by the targeted FPGA
device.
FPGA Master Serial Mode
In Master Serial mode, the FPGA automatically loads the
configuration bitstream in bit-serial form from external
memory synchronized by the configuration clock (CCLK)
generated by the FPGA. Upon power-up or reconfiguration,
the FPGA's mode select pins are used to select the Master
Serial configuration mode. Master Serial Mode provides a
simple configuration interface. Only a serial data line, a
clock line, and two control lines (INIT and DONE) are
required to configure an FPGA. Data from the PROM is
read out sequentially on a single data line (DIN), accessed
via the PROM's internal address counter which is
incremented on every valid rising edge of CCLK. The serial
bitstream data must be set up at the FPGA’s DIN input pin a
short time before each rising edge of the FPGA's internally
generated CCLK signal.
Typically, a wide range of frequencies can be selected for
the FPGA’s internally generated CCLK which always starts
Figure 5:
Design Revision Storage Examples
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(8 Mbits)
REV 3
(8 Mbits)
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(8 Mbits)
REV 1
(24 Mbits)
REV 0
(32 Mbits)
4 Design Revisions
(a) Design Revision storage examples for a single XCF32P PROM
3 Design Revisions
2 Design Revisions
1 Design Revision
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(16 Mbits)
REV 3
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(32 Mbits)
REV 0
(32 Mbits)
REV 1
(32 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(32 Mbits)
4 Design Revisions
(b) Design Revision storage examples spanning two XCF32P PROMs
3 Design Revisions
2 Design Revisions
1 Design Revision
PROM 0
PROM 0
PROM 0
PROM 0
PROM 0
PROM 0
PROM 0
PROM 0
PROM 0
PROM 0
REV 0
(32 Mbits)
REV 1
(32 Mbits)
PROM 1
PROM 1
PROM 1
PROM 1
PROM 1
ds123_20_102103
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