參數(shù)資料
型號(hào)： XCF08PVOG48
廠商： Xilinx, Inc.
英文描述： Platform Flash In-System Programmable Configuration PROMS
中文描述： 平臺(tái)Flash在系統(tǒng)可編程配置方案管理系統(tǒng)
文件頁(yè)數(shù)： 18/46頁(yè)
文件大?。?/td> 525K
代理商： XCF08PVOG48
Platform Flash In-System Programmable Configuration PROMS
DS123 (v2.9) May 09, 2006
www.xilinx.com
18
R
Figure 10:
Configuring in Slave SelectMAP Mode
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down externally. One option is shown.
4 The BUSY pin is only available with the XCFxxP Platform Flash PROM, and the connection is only required for high-
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
5 In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or, optionally, the
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XCFxxP PROM's CLKOUT signal
is used, then CLKOUT must be tied to a 4.7 K
Ω
resistor pulled up to V
CCO
.
6 For the XCFxxP the CF pin is a bidirectional pin. For the XCFxxP, if CF is not connected to PROGB, then it must be
tied to V
CCO
via a 4.7 k
Ω
pull-up resistor.
XCFxxP
Platform Flash
PROM
V
CCINT
V
CCO(2)
V
CCJ(2)
TDI
TMS
TCK
GND
D[0:7]
CLK
(5)
CE
CEO
OE/RESET
CF
(6)
BUSY
(4)
TDO
Xilinx FPGA
Slave SelectMAP
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
TDI
TMS
TCK
GND
MODE PINS
(1)
RDWR_B
CS_B
TDO
V
CCJ
V
CCO
V
CCINT
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
(4)
4
Ω
4
Ω
(1)
V
CCO(2)
...OPTIONAL
Slave FPGAs
with
identical
configurations
TDI
TMS
TCK
TDO
1K
Ω
1K
Ω
I/O
(3)
I/O
(3)
ds123_15_122105
External
(5)
Oscillator
相關(guān)PDF資料
PDF描述
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XCF16PFS48C Platform Flash In-System Programmable Configuration PROMS
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