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參數(shù)資料
| 型號： | XC9536-5PC44I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | XC9536 In-System Programmable CPLD |
| 中文描述： | XC9536在系統(tǒng)可編程的CPLD |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 165K |
| 代理商： | XC9536-5PC44I |
2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
36 macrocells with 800 usable gates
Available in small footprint packages
-
44-pin PLCC (34 user I/O pins)
-
44-pin VQFP (34 user I/O pins)
-
48-pin CSP (36 user I/O pins)
Optimized for high-performance 2.5V systems
-
Low power operation
-
Multi-voltage operation
Advanced system features
-
In-system programmable
-
Superior pin-locking and routability with
Fast CONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold circuitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
20 year data retention
-
ESD protection exceeding 2,000V
Pin-compatible with 3.3V-core XC9536XL device in the
44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages
Description
The XC9536XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See
Figure 2
for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
P
TOTAL
= P
INT
+ P
IO
= I
CCINT
x V
CCINT
+ P
IO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. P
IO
is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. I
CCINT
is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
I
CCINT
(taken from simulation) is:
I
CCINT
(mA) = MC
HS
(0.122 X PT
HS
+ 0.238) + MC
LP
(0.042 x
PT
LP
+ 0.171) + 0.04(MC
HS
+ MC
LP
) x f
MAX
x MC
TOG
where:
MC
HS
= # macrocells used in high speed mode
MC
LP
= #macrocells used in low power mode
PT
HS
= average p-terms used per high speed macrocell
PT
LP
= average p-terms used over low power macrocell
f
MAX
= max clocking frequency in the device
MC
TOG
= % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation.
Figure 1
shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note
XAPP361, “Planning for High Speed
XC9500XV Designs.”
0
XC9536XV High-performance
CPLD
DS053 (v2.6) April 15, 2005
0
1
Product Specification
R
Figure 1:
Typical I
CC
vs. Frequency for XC9536XV
Clock Frequency (MHz)
T
C
0
100
200
DS053_01_121501
60
20
120 MHz
200 MHz
30
L
ow Power
150
50
10
40
50
Hi
g
h Performance
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