參數(shù)資料
型號(hào)： XC95288XV-10TQ144C
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 9/14頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 2.5V ISP 144-TQFP
產(chǎn)品變化通告： Product Discontinuation Notice 14/May/2007
標(biāo)準(zhǔn)包裝： 60
系列： XC9500XV
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 10.0ns
電壓電源 - 內(nèi)部： 2.37 V ~ 2.62 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 288
門(mén)數(shù)： 6400
輸入/輸出數(shù)： 117
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤(pán)
其它名稱(chēng)： XC95288XV10TQ144C
XC95288XV High-Performance CPLD
4
DS050 (v3.0) June 25, 2007
Product Specification
R
Supported I/O Standards
The XC95288XV CPLD features both LVCMOS and LVTTL
I/O implementations. See Table 1 for I/O standard voltages.
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The ISE software automatically groups outputs with
matching IOSTANDARD settings into the same VCCIO bank
when no location constraints are specified. The default I/O
Standard for pads without IOSTANDARD attributes is
LVTTL for XC9500XV devices.
Absolute Maximum Ratings
Recommended Operation Conditions
Table 1: IOSTANDARD Options
IOSTANDARD
VCCIO
LVTTL
3.3V
LVCMOS2
2.5V
X25TO18
1.8V
Symbol
Description
Value
Units
VCC
Supply voltage relative to GND
–0.5 to 2.7
V
VCCIO
Supply voltage for output drivers
–0.5 to 3.6
V
VIN
Input voltage relative to GND(1)
–0.5 to 3.6
V
VTS
Voltage applied to 3-state output(1)
–0.5 to 3.6
V
TSTG
Storage temperature (ambient)
–65 to +150
oC
TJ
Junction temperature
+150
oC
Notes:
1.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3.
For solder specifications, see Xilinx Packaging.
Symbol
Parameter
Min
Max
Units
VCCINT
Supply voltage for internal logic
and input buffers
Commercial TA = 0oC to +70oC
2.37
2.62
V
Industrial TA = –40oC to +85oC
2.37
2.62
VCCIO
Supply voltage for output drivers for 3.3V operation
3.0
3.6
V
Supply voltage for output drivers for 2.5V operation
2.37
2.62
V
Supply voltage for output drivers for 1.8V operation
1.71
1.89
V
VIL
Low-level input voltage
0
0.8
V
VIH
High-level input voltage
1.7
3.6
V
VO
Output voltage
0
VCCIO
V
Product Obsolete/Under Obsolescence
相關(guān)PDF資料
PDF描述
AP1084DL-13 IC REG LDO ADJ 5A TO-252
TPSB474M035R4000 CAP TANT 0.47UF 35V 20% 1210
A181M15X7RL5UAA CAP CER 180PF 500V 20% X7R AXIAL
GEC08DRYN-S734 CONN EDGECARD 16POS DIP .100 SLD
GEC05DREI CONN EDGECARD 10POS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC95288XV-10TQ144I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:High-Performance CPLD
XC95288XV-5CS280C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:High-Performance CPLD
XC95288XV-5CS280I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:High-Performance CPLD
XC95288XV-5FG256C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:High-Performance CPLD
XC95288XV-5FG256I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:High-Performance CPLD
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*