- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19485 > XC95144XL-7TQ144C (Xilinx Inc)IC 3.3V CPLD COMM. TEMP 144TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XC95144XL-7TQ144C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 3.3V CPLD COMM. TEMP 144TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | XC9500XL |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 8 |
| 宏單元數(shù)： | 144 |
| 門數(shù)： | 3200 |
| 輸入/輸出數(shù)： | 117 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
| 其它名稱： | Q1039179 |
DS056 (v2.0) April 3, 2007
1
Product Specification
1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
144 macrocells with 3,200 usable gates
Available in small footprint packages
-
100-pin TQFP (81 user I/O pins)
-
144-pin TQFP (117 user I/O pins)
-
144-CSP (117 user I/O pins)
-
Pb-free available for all packages
Optimized for high-performance 3.3V systems
-
Low power operation
-
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
-
3.3V or 2.5V output capability
-
Advanced 0.35 micron feature size CMOS
Fast FLASH technology
Advanced system features
-
In-system programmable
-
Superior pin-locking and routability with
Fast CONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin with local
inversion
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold circuitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
Endurance exceeding 10,000 program/erase
cycles
-
20 year data retention
-
ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC95144 device in the
100-pin TQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95144XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of eight
54V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 5 ns. See Figure 2 for overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC95144XL High Performance
CPLD
DS056 (v2.0) April 3, 2007
00
Product Specification
R
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GBC25DRXN | CONN EDGECARD 50POS DIP .100 SLD |
| GBC25DRXH | CONN EDGECARD 50POS DIP .100 SLD |
| AGM24DTMH | CONN EDGECARD 48POS R/A .156 SLD |
| A-DF09AA-WP-R | CONN DSUB IP67 FMAL PCB R/A 9POS |
| ECC05DRXN | CONN EDGECARD 10POS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC95144XL-7TQ144C0768 | 制造商:Xilinx 功能描述: |
| XC95144XL-7TQ144C0962 | 制造商:Xilinx 功能描述:XLXXC95144XL-7TQ144C0962 IC SYSTEM GATE |
| XC95144XL-7TQ144I | 功能描述:IC CPLD 144MCELL 7.5NS 144TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500XL 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95144XL-7TQG100C | 功能描述:IC CPLD 3.2K 144MCELL 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500XL 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95144XL-7TQG100C0962 | 制造商:Xilinx 功能描述:XLXXC95144XL-7TQG100C0962 IC SYSTEM GATE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。