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參數(shù)資料
| 型號： | XC95108 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 74K |
| 代理商： | XC95108 |
XAPP073 January, 1998 (Version 1.3)
2-19
2
Summary
This application note will help designers understand the XC9500 architecture and how to get the best performance from
these devices.
Xilinx Family
XC9500
Introduction
To get the best performance from any CPLD, the designer
must be aware of its internal architecture and how the vari-
ous device features work together. This application note
provides useful examples and practical details for creating
successful designs. These design techniques apply to all
XC9500 devices because the architecture is uniform
across the family.
XC9500 Architecture
The XC9500 architecture is comprised of multiple identical
function blocks internally connected by a fully populated
FastCONNECT switch matrix. The XC9500 function block
has 18 macrocells per block and supports pin-to-pin
speeds as fast as 5 ns, with clock rates up to 125 MHz. I/O
signals can interface with 5 volt, 3.3 volt, or both levels.
Figure 1
shows the XC9500 architecture. Note the regular
structure of high speed function blocks centrally connected
by the FastCONNECT matrix and surrounded by pins. Sig-
nals enter and exit on the pins, form logic operations within
the function blocks, and form connections and logic opera-
tions within FastCONNECT. Each of these features is dis-
cussed in the following sections to highlight key
functionality.
Interconnect Within Function Blocks
Function blocks (FBs) have 36 input sites. The FBs receive
signals from the FastCONNECT matrix and input pins. The
logic blocks generate 18 signals per FB from the 18 macro-
cells in each block, and each macrocell signal can drive its
own dedicated I/O pin or feedback by entering the Fast-
CONNECT matrix. Additional high speed local paths exist
within the FB.
Figure 1: XC9500 Architecture
Designing with XC9500 CPLDs
XAPP073 January, 1998 (Version 1.3)
Application Note
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
36
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2 or 4
1
I/O
I/O
I/O
I/O
3
X5877
Function
Block 2
36
Function
Block 3
36
18
18
18
18
Function
Block N
36
F
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| XC95108-10PCG84C | 制造商:Xilinx 功能描述:XLXXC95108-10PCG84C IC SYSTEM GATE |
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| XC95108-10PQ100C0586 | 制造商:Xilinx 功能描述: |
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