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參數資料
| 型號： | XC95108-7TQ100I |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | XC95108 In-System Programmable CPLD |
| 中文描述： | FLASH PLD, 7.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 189K |
| 代理商： | XC95108-7TQ100I |
DS066 (v4.4) April 3, 2006
1
Product Specification
2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
7.5 ns pin-to-pin logic delays on all pins
fCNT to 125 MHz
108 macrocells with 2,400 usable gates
Up to 108 user I/O pins
5V in-system programmable
-
Endurance of 10,000 program/erase cycles
-
Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
90 product terms drive any or all of 18 macrocells
within Function Block
-
Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 84-pin PLCC, 100-pin PQFP, 100-pin
TQFP, and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95108 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95108
device.
0
XC95108 In-System
Programmable CPLD
DS066 (v4.4) April 3, 2006
05
Product Specification
R
Figure 1: Typical ICC vs. Frequency for XC95108
Clock Frequency (MHz)
Typical
I
CC
(mA)
050
100
(180)
(250)
(170)
200
300
100
High Performance
Low Power
DS066_01_110501
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| XC95108-7TQG100C | 功能描述:IC CPLD 108MCRCELL 7NS 100TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:XC9500 標準包裝:24 系列:CoolRunner II 可編程類型:系統內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數目:24 宏單元數:384 門數:9000 輸入/輸出數:173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95108PQ160AE | 制造商:XILINX 功能描述:NEW |
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| XC9510A1333 | 制造商:TOREX 制造商全稱:Torex Semiconductor 功能描述:Synchronous Step-Down DC/DC Converter With Built-In LDO Regulator Plus Voltage Detector |
| XC9510A1334 | 制造商:TOREX 制造商全稱:Torex Semiconductor 功能描述:Synchronous Step-Down DC/DC Converter With Built-In LDO Regulator Plus Voltage Detector |
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