![](http://datasheet.mmic.net.cn/370000/XC9303_datasheet_16740920/XC9303_5.png)
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OPERATIONAL DESCRIPTION
<Error Amp>
The Error Amplifier is designed to monitor the output voltage and it compares the feedback voltage (FB) with the reference voltage. In response to
feedback of a voltage lower than the reference voltage, the output voltage of the error amp. decreases.
<OSC Generator>
This circuit generates the oscillation frequency which in turn generates the source clock.
<Ramp Wave Generator>
<PWM Comparator>
The PWM Comparator compares outputs from the Error Amp. and saw-tooth waveform. When the voltage from the Error Amp's output is low, the
external switch will be set to ON.
<PWM/PFM Controller>
This circuit generates PFM pulses.
Control can be switched between PWM control and PWM/PFM automatic switching control using external signals.
The PWM/PFM automatic switching mode is selected when the voltage of the PWM pin is less than 0.2V, and the control switches between PWM and
PFM automatically depending on the load. As the PFM circuit generates pulses based on outputs from the PWM comparator, shifting between modes
occurs smoothly. PWM control mode is selected when the voltage of the PWM pin is more than 0.65V. Noise is easily reduced with PWM control since
the switching frequency is fixed.
Control suited to the application can easily be selected which is useful in audio applications, for example, where traditionally, efficiencies have been
sacrificed during stand-by as a result of using PWM control (due to the noise problems associated with the PFM mode in stand-by).
<Synchronous, blank logic>
The synchronous, blank logic circuit is to prevent penetration of the transistor connected to EXT1 and EXT2.
<Vref with Soft Start>
The reference voltage, Vref (FB pin voltage)=0.9V, is adjusted and fixed by laser trimming (for output voltage settings, please refer to page 8). To protect
against inrush current, when the power is switched on, and also to protect against voltage overshoot, soft-start time is set internally to 10ms. It should
be noted, however, that this circuit does not protect the load capacitor (CL) from inrush current. With the Vref voltage limited and depending upon the
input to the error amps, the operation maintains a balance between the two inputs of the error amps and controls the EXT pin's ON time so that it doesn't
increase more than is necessary.
<Chip Enable Function>
This function controls the operation and shutdown of the IC. When the voltage of the CE pin is 0.2V or less, the mode will be chip disable, the channel's
operations will stop. The EXT1 pin will be kept at a highlevel (the external P-type MOSFET will be OFF) and the EXT2 pin will be kept at a lowlevel (the
external N-type MOSFET will be OFF). When CE pin is in a state of chip disable, current consumption will be no more than 3.0
μ
A.
When the CE pin's voltage is 0.65V or more, the mode will be chip enable and operations will recommence. With soft-start, 95% of the set output
voltage will be reached within 10mS (TYP) from the moment of chip enable.
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The XC9303 series are synchronous step-up & down DC/DC converter controller ICs with built-in high speed, low ON resistance drivers.
The Ramp Wave Generator generates a saw-tooth waveform based on outputs from the Phase Shift Generator.
XC9303 Series
High Efficiency, Synchronous
Step-Up & Down DC / DC Controller ICs
Semiconductor Ltd.