參數(shù)資料
型號： XC888LM
廠商： INFINEON TECHNOLOGIES AG
元件分類： 8位微控制器
英文描述： 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述： 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù)： 40/119頁
文件大?。?/td> 895K
代理商： XC888LM
XC886/888CLM
Functional Description
Data Sheet
Prelimary
36
V0.1, 2006-02
RMAP = 0
,
Page 4
CA
H
ADC_RCR0
Result Control Register 0
Reset: 00
H
Bit Field
VFCTR
WFR
FEN
IEN
0
DRCT
R
rw
DRCT
R
rw
DRCT
R
rw
DRCT
R
rw
VFC0
w
Type
Bit Field
rw
rw
rw
FEN
rw
IEN
r
0
CB
H
ADC_RCR1
Result Control Register 1
Reset: 00
H
VFCTR
WFR
Type
Bit Field
rw
rw
rw
FEN
rw
IEN
r
0
CC
H
ADC_RCR2
Result Control Register 2
Reset: 00
H
VFCTR
WFR
Type
Bit Field
rw
rw
rw
FEN
rw
IEN
r
0
CD
H
ADC_RCR3
Result Control Register 3
Reset: 00
H
VFCTR
WFR
Type
Bit Field
Type
rw
rw
rw
rw
r
CE
H
ADC_VFCR
Valid Flag Clear Register
Reset: 00
H
0
r
VFC3
w
VFC2
w
VFC1
w
RMAP = 0
,
Page 5
CA
H
ADC_CHINFR
Channel Interrupt Flag Register
Reset: 00
H
Bit Field
CHINF
7
rh
CHINC
7
w
CHINS
7
w
CHINP
7
rw
EVINF
7
rh
EVINC
7
w
EVINS
7
w
EVINP
7
rw
CHINF
6
rh
CHINC
6
w
CHINS
6
w
CHINP
6
rw
EVINF
6
rh
EVINC
6
w
EVINS
6
w
EVINP
6
rw
CHINF
5
rh
CHINC
5
w
CHINS
5
w
CHINP
5
rw
EVINF
5
rh
EVINC
5
w
EVINS
5
w
EVINP
5
rw
CHINF
4
rh
CHINC
4
w
CHINS
4
w
CHINP
4
rw
EVINF
4
rh
EVINC
4
w
EVINS
4
w
EVINP
4
rw
CHINF
3
rh
CHINC
3
w
CHINS
3
w
CHINP
3
rw
CHINF
2
rh
CHINC
2
w
CHINS
2
w
CHINP
2
rw
CHINF
1
rh
CHINC
1
w
CHINS
1
w
CHINP
1
rw
EVINF
1
rh
EVINC
1
w
EVINS
1
w
EVINP
1
rw
CHINF
0
rh
CHINC
0
w
CHINS
0
w
CHINP
0
rw
EVINF
0
rh
EVINC
0
w
EVINS
0
w
EVINP
0
rw
Type
Bit Field
CB
H
ADC_CHINCR
Channel Interrupt Clear Register
Reset: 00
H
Type
Bit Field
CC
H
ADC_CHINSR
Channel Interrupt Set Register
Reset: 00
H
Type
Bit Field
CD
H
ADC_CHINPR
Channel Interrupt Node Pointer
Register
Reset: 00
H
Type
Bit Field
CE
H
ADC_EVINFR
Event Interrupt Flag Register
Reset: 00
H
0
Type
Bit Field
r
0
CF
H
ADC_EVINCR
Event Interrupt Clear Flag Register
Reset: 00
H
Type
Bit Field
r
0
D2
H
ADC_EVINSR
Event Interrupt Set Flag Register
Reset: 00
H
Type
Bit Field
r
0
D3
H
ADC_EVINPR
Event Interrupt Node Pointer Register
Reset: 00
H
Type
r
RMAP = 0
,
Page 6
CA
H
ADC_CRCR1
Conversion Request Control Register 1
Reset: 00
Bit Field
CH7
CH6
CH5
CH4
0
Type
Bit Field
rwh
CHP7
rwh
CHP6
rwh
CHP5
rwh
CHP4
r
0
CB
H
ADC_CRPR1
Conversion Request Pending
Register 1
Reset: 00
H
Type
Bit Field
rwh
Rsv
rwh
LDEV
rwh
CLR
PND
w
rwh
SCAN
r
CC
H
ADC_CRMR1
Conversion Request Mode Register 1
Reset: 00
H
ENSI
ENTR
ENGT
Type
Bit Field
Type
r
w
rw
rw
0
r
rw
rw
CD
H
ADC_QMR0
Queue Mode Register 0
Reset: 00
H
CEV
w
TREV FLUSH CLRV
w
w
ENTR
rw
ENGT
rw
w
Table 11
Addr
ADC Register Overview
(cont’d)
Register Name
Bit
7
6
5
4
3
2
1
0
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