參數(shù)資料
型號(hào): XC850DECZT50BUR2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 33/72頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 50MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 500
系列: MPC8xx
處理器類(lèi)型: 32-位 MPC8xx PowerQUICC
速度: 50MHz
電壓: 3.3V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 帶卷 (TR)
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
39
IEEE 1149.1 Electrical Specifications
Figure 33 provides the reset timing for the debug port configuration.
Figure 33. Reset Timing—Debug Port Configuration
7
IEEE 1149.1 Electrical Specifications
Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37.
Table 12. JTAG Timing
Num
Characteristic
50 MHz
66MHz
80 MHz
Unit
Min
Max
Min
Max
Min
Max
J82
TCK cycle time
100.00
100.00
100.00
ns
J83
TCK clock pulse width measured at 1.5 V
40.00
40.00
40.00
ns
J84
TCK rise and fall times
0.00
10.00
0.00
10.00
0.00
10.00
ns
J85
TMS, TDI data setup time
5.00
5.00
5.00
ns
J86
TMS, TDI data hold time
25.00
25.00
25.00
ns
J87
TCK low to TDO data valid
27.00
27.00
27.00
ns
J88
TCK low to TDO data invalid
0.00
0.00
0.00
ns
J89
TCK low to TDO high impedance
20.00
20.00
20.00
ns
J90
TRST assert time
100.00
100.00
100.00
ns
J91
TRST setup time to TCK low
40.00
40.00
40.00
ns
J92
TCK falling edge to output valid
50.00
50.00
50.00
ns
J93
TCK falling edge to output valid out of high
impedance
50.00
50.00
50.00
ns
J94
TCK falling edge to output high impedance
50.00
50.00
50.00
ns
J95
Boundary scan input valid to TCK rising edge
50.00
50.00
50.00
ns
J96
TCK rising edge to boundary scan input invalid
50.00
50.00
50.00
ns
CLKOUT
SRESET
DSCK, DSDI
R70
R82
R80
R81
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