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    參數(shù)資料
    

    


    


    
型號：
XC6SLX100T-3FG484I

    

    
廠商：
Xilinx Inc

    

    
文件頁數(shù)：
58/89頁

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA SPARTAN 6 484FGGBGA

    

    
標準包裝：
60

    

    
系列：
Spartan® 6 LXT

    

    
LAB/CLB數(shù)：
7911
    		

    

    
邏輯元件/單元數(shù)：
101261
    		

    

    
RAM 位總計：
4939776
    		

    

    
輸入/輸出數(shù)：
296
    		

    

    
電源電壓：
1.14 V ~ 1.26 V
    		

    

    
安裝類型：
表面貼裝
    		

    

    
工作溫度：
-40°C ~ 100°C
    		

    

    
封裝/外殼：
484-BBGA
    		

    

    
供應商設備封裝：
484-FBGA
    		

    

    

    

	
    
    
    

    
    
	
    Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
    DS162 (v3.0) October 17, 2011
    Product Specification
    61
    Table 56: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP(1)
    Symbol
    Description
    Speed Grade
    Units
    -3
    -3N
    -2
    -1L
    Min
    Max
    Min
    Max
    Min
    Max
    Min
    Max
    Output Frequency Ranges
    CLKOUT_FREQ_FX
    Frequency for the CLKFX and
    CLKFX180 outputs
    537553755333
    5200
    MHz
    Output Clock Jitter(2)(3)
    CLKOUT_PER_JITT_FX
    Period jitter at the CLKFX and
    CLKFX180 outputs. When
    CLKIN < 20 MHz
    Use the Clocking Wizard
    ps
    Period jitter at the CLKFX and
    CLKFX180 outputs. When
    CLKIN > 20 MHz
    Typical = ±(1% of CLKFX period + 100)
    ps
    Duty Cycle(4)(5)
    CLKOUT_DUTY_CYCLE_FX
    Duty cycle precision for the CLKFX
    and CLKFX180 outputs including the
    BUFGMUX and clock tree duty-cycle
    distortion
    Maximum = ±(1% of CLKFX period + 350)
    ps
    Phase Alignment(5)
    CLKOUT_PHASE_FX
    Phase offset between the DFS
    CLKFX output and the DLL CLK0
    output when both the DFS and DLL
    are used
    –
    ±200
    –
    ±200
    –
    ±200
    –
    ±250
    ps
    CLKOUT_PHASE_FX180
    Phase offset between the DFS
    CLKFX180 output and the DLL CLK0
    output when both the DFS and DLL
    are used
    Maximum = ±(1% of CLKFX period + 200)
    ps
    LOCKED Time
    LOCK_FX(2)
    When FCLKIN < 50 MHz, the time
    from deassertion at the DCM’s reset
    input to the rising transition at its
    LOCKED output. The DFS asserts
    LOCKED when the CLKFX and
    CLKFX180 signals are valid. When
    using both the DLL and the DFS, use
    the longer locking time.
    –
    5–5–5–
    5
    ms
    When FCLKIN > 50 MHz, the time
    from deassertion at the DCM’s reset
    input to the rising transition at its
    LOCKED output. The DFS asserts
    LOCKED when the CLKFX and
    CLKFX180 signals are valid. When
    using both the DLL and the DFS, use
    the longer locking time.
    –0.45–0.45–0.45–
    0.60
    ms
    Notes:
    1.
    The values in this table are based on the operating conditions described in Table 2 and Table 55.
    2.
    For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.
    3.
    Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
    strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on
    the system application.
    4.
    The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.
    5.
    Some duty cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum
    CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and
    1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps.
    
    
    
    
    
    


    


    

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XC6SLX100T-3FGG484C
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