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| 型號(hào)： | XC68C812A4PVE5 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 128/242頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MCU 16BIT LOW VOLT 112-LQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | HC12 |
| 核心處理器： | CPU12 |
| 芯體尺寸： | 16-位 |
| 速度： | 5MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 83 |
| 程序存儲(chǔ)器容量： | 4KB（4K x 8） |
| 程序存儲(chǔ)器類型： | EEPROM |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 112-LQFP |
| 包裝： | 托盤 |
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Background Debug Mode (BDM)
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor
213
Figure 17-1 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target M68HC12 MCU.
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling
edge to where the target perceives the beginning of the bit time. Ten target E cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Since the target does not drive the BKGD
pin during this period, there is no need to treat the line as an open-drain signal during host-to-target
transmissions.
Figure 17-1. BDM Host-to-Target Serial Bit Timing
Figure 17-2 shows the host receiving a logic 1 from the target MC68HC812A4 MCU. Since the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target E cycles). The host must release the low drive
before the target MCU drives a brief active-high speed-up pulse seven cycles after the perceived start of
the bit time. The host should sample the bit level about 10 cycles after it started the bit time.
Figure 17-3 shows the host receiving a logic 0 from the target MC68HC812A4 MCU. Since the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target MC68HC812A4 finishes it. Since the target wants the host to receive a logic 0, it drives the BKGD
pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge. The host samples the
bit level about 10 cycles after starting the bit time.
17.3.2 Enabling BDM Firmware Commands
BDM is available in all operating modes, but must be made active before firmware commands can be
executed. BDM is enabled by setting the ENBDM bit in the BDM STATUS register via the single wire
interface (using a hardware command; WRITE_BD_BYTE at $FF01). BDM must then be activated to map
BDM registers and ROM to addresses $FF00 to $FFFF and to put the MCU in active background mode.
After the firmware is enabled, BDM can be activated by the hardware BACKGROUND command, by the
BDM tagging mechanism, or by the CPU BGND instruction. An attempt to activate BDM before firmware
has been enabled causes the MCU to resume normal instruction execution after a brief delay.
EARLIEST START
TARGET SENSES BIT LEVEL
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
E CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED START
OF BIT TIME
OF NEXT BIT
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