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參數(shù)資料
型號(hào): XC5VTX150T-1FFG1156C
廠(chǎng)商: Xilinx Inc
文件頁(yè)數(shù): 76/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX5TXT 150K 1156FBGA
產(chǎn)品培訓(xùn)模塊: PCI Express and Virtex® -5 FPGAs
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 TXT
LAB/CLB數(shù): 11600
邏輯元件/單元數(shù): 148480
RAM 位總計(jì): 8404992
輸入/輸出數(shù): 360
電源電壓: 0.95 V ~ 1.05 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1156-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1156-FCBGA(35x35)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
78
TPSPLL0/ TPHPLL0
No Delay Global Clock and IFF(2) with PLL in
Source-Synchronous Mode
XC5VTX150T
N/A
–0.31
1.41
–0.29
1.47
ns
XC5VTX240T
N/A
–0.31
1.61
–0.29
1.66
ns
XC5VFX30T
–0.10
1.40
–0.09
1.46
–0.08
1.55
ns
XC5VFX70T
–0.12
1.38
–0.10
1.44
–0.09
1.53
ns
XC5VFX100T
–0.18
1.51
–0.18
1.60
–0.18
1.71
ns
XC5VFX130T
–0.12
1.66
–0.11
1.76
–0.09
1.92
ns
XC5VFX200T
N/A
–0.12
1.94
–0.10
2.06
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2.
IFF = Input Flip-Flop or Latch.
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 95: Global Clock Setup and Hold With PLL in Source-Synchronous Mode (Cont’d)
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
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