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  • 參數(shù)資料
    型號: XC5VSX50T-3FFG1136C
    廠商: Xilinx Inc
    文件頁數(shù): 54/91頁
    文件大?。?/td> 0K
    描述: IC FPGA VIRTEX-5 50K 1136FBGA
    產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
    標(biāo)準(zhǔn)包裝: 1
    系列: Virtex®-5 SXT
    LAB/CLB數(shù): 4080
    邏輯元件/單元數(shù): 52224
    RAM 位總計(jì): 4866048
    輸入/輸出數(shù): 480
    電源電壓: 0.95 V ~ 1.05 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 1136-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 1136-FCBGA
    配用: 568-5088-ND - BOARD DEMO DAC1408D750
    122-1796-ND - EVALUATION PLATFORM VIRTEX-5
    Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
    DS202 (v5.3) May 5, 2010
    Product Specification
    58
    Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
    Symbol
    Description
    Speed Grade
    Units
    -3
    -2
    -1
    Outputs Clocks (Low Frequency Mode)
    F1XMRMIN
    CLK0, CLK90, CLK180, CLK270
    19.00
    MHz
    F1XMRMAX
    32.00
    MHz
    F2XMRMIN
    CLK2X, CLK2X180
    38.00
    MHz
    F2XMRMAX
    64.00
    MHz
    FDLLMRMIN
    CLKDV
    1.191.191.19
    MHz
    FDLLMRMAX
    21.34
    MHz
    FFXMRMIN
    CLKFX, CLKFX180
    19.00
    MHz
    FFXMRMAX
    40.00
    MHz
    Input Clocks (Low Frequency Mode)
    FCLKINDLLMRMIN
    CLKIN (using DLL outputs)(1, 3, 4)
    19.00
    MHz
    FCLKINDLLMRMAX
    32.00
    MHz
    FCLKINFXMRMIN
    CLKIN (using DFS outputs only)(2, 3, 4)
    1.00
    MHz
    FCLKINFXMRMAX
    40.00
    MHz
    FPSCLKMRMIN
    PSCLK
    1.00
    KHz
    FPSCLKMRMAX
    300.00
    270.00
    240.00
    MHz
    Notes:
    1.
    DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
    2.
    DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
    3.
    When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
    frequency.
    4.
    When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within ±5% (45/55
    to 55/45).
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