參數(shù)資料
型號: XC5VLX85T-3FFG1136C
廠商: Xilinx Inc
文件頁數(shù): 50/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 85K 1136FBGA
產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
標準包裝: 1
系列: Virtex®-5 LXT
LAB/CLB數(shù): 6480
邏輯元件/單元數(shù): 82944
RAM 位總計: 3981312
輸入/輸出數(shù): 480
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1136-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1136-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
54
Table 73: Regional Clock Switching Characteristics (BUFR)
Symbol
Description
Devices
Speed Grade
Units
-3
-2
-1
TBRCKO_O
Clock to out delay from
I to O
LX20T
N/A
0.79
0.90
ns
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX100T, and
FX130T
0.56
0.59
0.67
ns
FX30T
0.72
0.78
0.86
ns
FX70T
0.69
0.74
0.83
ns
LX155 and LX155T
0.73
0.80
0.90
ns
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A
0.59
0.67
ns
TBRCKO_O_BYP
Clock to out delay from I to
O with Divide Bypass
attribute set
LX20T
N/A
0.29
0.30
ns
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX30T, FX70T,
FX100T, and FX130T
0.23
0.24
0.26
ns
LX155 and LX155T
0.24
0.26
0.30
ns
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A
0.24
0.26
ns
TBRDO_CLRO
Propagation delay from
CLR to O
All
0.61
0.70
0.82
ns
Maximum Frequency
FMAX
Regional clock tree
(BUFR)
All
300
250
MHz
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