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    參數(shù)資料
    型號: XC5VLX85-1FFG676C
    廠商: Xilinx Inc
    文件頁數(shù): 9/91頁
    文件大?。?/td> 0K
    描述: IC FPGA VIRTEX-5 85K 676FBGA
    標(biāo)準(zhǔn)包裝: 1
    系列: Virtex®-5 LX
    LAB/CLB數(shù): 6480
    邏輯元件/單元數(shù): 82944
    RAM 位總計: 3538944
    輸入/輸出數(shù): 440
    電源電壓: 0.95 V ~ 1.05 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 676-BBGA,F(xiàn)CBGA
    供應(yīng)商設(shè)備封裝: 676-FCBGA(27x27)
    配用: 568-5088-ND - BOARD DEMO DAC1408D750
    Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
    DS202 (v5.3) May 5, 2010
    Product Specification
    17
    Table 33: GTP_DUAL Tile User Clock Switching Characteristics(1)
    Symbol
    Description
    Conditions
    Speed Grade
    Units
    -3
    -2
    -1
    FTXOUT
    TXOUTCLK maximum frequency
    375
    320
    MHz
    FRXREC
    RXRECCLK maximum frequency
    375
    320
    MHz
    TRX
    RXUSRCLK maximum frequency
    375
    320
    MHz
    TRX2
    RXUSRCLK2 maximum frequency
    RXDATAWIDTH = 0
    350
    320
    MHz
    RXDATAWIDTH = 1
    187.5
    160
    MHz
    TTX
    TXUSRCLK maximum frequency
    375
    320
    MHz
    TTX2
    TXUSRCLK2 maximum frequency
    TXDATAWIDTH = 0
    350
    320
    MHz
    TXDATAWIDTH = 1
    187.5
    160
    MHz
    Notes:
    1.
    Clocking must be implemented as described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide
    Table 34: GTP_DUAL Tile Transmitter Switching Characteristics
    Symbol
    Description
    Min
    Typ
    Max
    Units
    FGTPTX
    Serial data rate range
    0.1
    FGTPMAX
    Gb/s
    TRTX
    TX Rise time
    140
    ps
    TFTX
    TX Fall time
    120
    ps
    TLLSKEW
    TX lane-to-lane skew(1)
    855
    ps
    VTXOOBVDPP
    Electrical idle amplitude
    20
    mV
    TTXOOBTRANS
    Electrical idle transition time
    40
    ns
    TJ3.75
    Total Jitter(2)
    3.75 Gb/s
    0.35
    UI
    DJ3.75
    Deterministic Jitter(2)
    0.19
    UI
    TJ3.2
    Total Jitter(2)
    3.20 Gb/s
    0.35
    UI
    DJ3.2
    Deterministic Jitter(2)
    0.19
    UI
    TJ2.5
    Total Jitter(2)
    2.50 Gb/s
    0.30
    UI
    DJ2.5
    Deterministic Jitter(2)
    0.14
    UI
    TJ2.0
    Total Jitter(2)
    2.00 Gb/s
    0.30
    UI
    DJ2.0
    Deterministic Jitter(2)
    0.14
    UI
    TJ1.25
    Total Jitter(2)
    1.25 Gb/s
    0.20
    UI
    DJ1.25
    Deterministic Jitter(2)
    0.10
    UI
    TJ1.00
    Total Jitter(2)
    1.00 Gb/s
    0.20
    UI
    DJ1.00
    Deterministic Jitter(2)
    0.10
    UI
    TJ500
    Total Jitter(2)
    500 Mb/s
    0.10
    UI
    DJ500
    Deterministic Jitter(2)
    0.04
    UI
    TJ100
    Total Jitter(2)
    100 Mb/s
    0.02
    UI
    DJ100
    Deterministic Jitter(2)
    0.01
    UI
    Notes:
    1.
    Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.
    2.
    Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.
    3.
    All jitter values are based on a Bit-Error Ratio of 1e–12.
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