參數(shù)資料
型號: XC5VFX200T-1FF1738CES
廠商: Xilinx Inc
文件頁數(shù): 82/91頁
文件大小: 0K
描述: IC FPGA V5 FX ES 200K 1738FBGA
標準包裝: 1
系列: Virtex®-5 FXT
LAB/CLB數(shù): 15360
邏輯元件/單元數(shù): 196608
RAM 位總計: 16809984
輸入/輸出數(shù): 960
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1738-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1738-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-AFX-FF1738-500-G-ND - BOARD DEV VIRTEX 5 FF1738
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
83
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 98: Duty Cycle Distortion and Clock-Tree Skew
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
TDCD_CLK
Global Clock Tree Duty Cycle Distortion(1)
All
0.12
ns
TCKSKEW
Global Clock Tree Skew(2)
XC5VLX20T
N/A
0.24
0.25
ns
XC5VLX30
0.21
0.22
ns
XC5VLX30T
0.21
0.22
ns
XC5VLX50
0.26
0.27
0.28
ns
XC5VLX50T
0.26
0.27
0.28
ns
XC5VLX85
0.42
0.43
0.45
ns
XC5VLX85T
0.42
0.43
0.45
ns
XC5VLX110
0.48
0.50
0.51
ns
XC5VLX110T
0.48
0.50
0.51
ns
XC5VLX155
0.82
0.85
0.88
ns
XC5VLX155T
0.82
0.85
0.88
ns
XC5VLX220
N/A
1.07
1.10
ns
XC5VLX220T
N/A
1.07
1.10
ns
XC5VLX330
N/A
1.25
1.29
ns
XC5VLX330T
N/A
1.25
1.29
ns
XC5VSX35T
0.38
0.39
ns
XC5VSX50T
0.43
0.44
0.45
ns
XC5VSX95T
N/A
0.72
0.74
ns
XC5VSX240T
N/A
1.32
1.36
ns
XC5VTX150T
N/A
0.70
0.73
ns
XC5VTX240T
N/A
0.97
1.00
ns
XC5VFX30T
0.34
0.35
ns
XC5VFX70T
0.41
0.42
0.43
ns
XC5VFX100T
0.82
0.84
0.86
ns
XC5VFX130T
0.82
0.84
0.86
ns
XC5VFX200T
N/A
1.24
1.29
ns
TDCD_BUFIO
I/O clock tree duty cycle distortion
All
0.10
ns
TBUFIOSKEW
I/O clock tree skew across one clock region
All
0.07
0.08
ns
TDCD_BUFR
Regional clock tree duty cycle distortion
All
0.25
ns
Notes:
1.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2.
The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to the application.
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