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參數(shù)資料
| 型號： | XC56L307VL150 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-MABGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 系列： | DSP563xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SSI，SCI |
| 時(shí)鐘速率： | 150MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 576kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 托盤 |
DSP56L307 Product Brief, Rev. 2
2
Freescale Semiconductor
Features
Table 1 lists the features of the DSP56L307 device.
Table 1. DSP56L307 Features
Feature
Description
High-Performance
DSP56300 Core
160 million multiply-accumulates per second (MMACS) (321 MMACS using the EFCOP in filtering
applications) with a 160 MHz clock at 1.8 V core and 3.3 V I/O
Object code compatible with the DSP56000 core with highly parallel instruction set
Data arithmetic logic unit (Data ALU) with fully pipelined 24
× 24-bit parallel multiplier-accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
Hardware debugging support including on-chip emulation (OnCE) module, Joint Test Action Group (JTAG)
test access port (TAP)
Enhanced Filter
Coprocessor (EFCOP)
Internal 24
× 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
Operation at the same frequency as the core (up to 160 MHz)
Support for a variety of filter modes, some of which are optimized for cellular base station applications:
Real finite impulse response (FIR) with real taps
Complex FIR with complex taps
Complex FIR generating pure real or pure imaginary outputs alternately
A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
Direct form 2 (DFII) IIR filter
Four scaling factors (1, 4, 8, 16) for IIR output
Adaptive FIR filter with true least mean square (LMS) coefficient updates
Adaptive FIR filter with delayed LMS coefficient updates
Internal Peripherals
Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
Internal Memories
192
× 24-bit bootstrap ROM
192 K
× 24-bit RAM total
Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
:
Program RAM
Size
Instruction
Cache Size
X Data RAM
Size*
Y Data RAM
Size*
Instruction
Cache
Switch
Mode
MSW1
MSW0
16 K
× 24-bit
0
24 K
× 24-bit
24 K
× 24-bit
disabled
0/1
15 K
× 24-bit
1024
× 24-bit
24 K
× 24-bit
24 K
× 24-bit
enabled
disabled
0/1
48 K
× 24-bit
0
8 K
× 24-bit
8 K
× 24-bit
disabled
enabled
0
47 K
× 24-bit
1024
× 24-bit
8 K
× 24-bit
8 K
× 24-bit
enabled
0
40 K
× 24-bit
0
12 K
× 24-bit
12 K
× 24-bit
disabled
enabled
0
1
39 K
× 24-bit
1024
× 24-bit
12 K
× 24-bit
12 K
× 24-bit
enabled
0
1
32 K
× 24-bit
0
16 K
× 24-bit
16 K
× 24-bit
disabled
enabled
1
0
31 K
× 24-bit
1024
× 24-bit
16 K
× 24-bit
16 K
× 24-bit
enabled
1
0
24 K
× 24-bit
0
20 K
× 24-bit
20 K
× 24-bit
disabled
enabled
1
23 K
× 24-bit
1024
× 24-bit
20 K
× 24-bit
20 K
× 24-bit
enabled
1
*Includes 4 K
× 24-bit shared memory (that is, memory shared by the core and the EFCOP)
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