
R
November 5, 1998 (Version 5.2)
7-133
XC5200 Series Field Programmable Gate Arrays
7
Device-Specific Pinout Tables
Device-specific tables include all packages for each XC5200-Series device. They follow the pad locations around the die,
and include boundary scan register locations.
Pin Locations for XC5202 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the
availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
Description
VQ64*
PC84
PQ100
VQ100
TQ144
PG156
Boundary Scan Order
VCC
-
2
92
89
128
H3
-
1.
I/O (A8)
57
3
93
90
129
H1
51
2.
I/O (A9)
58
4
94
91
130
G1
54
3.
I/O
-
95
92
131
G2
57
4.
I/O
-
96
93
132
G3
63
5.
I/O (A10)
-
5
97
94
133
F1
66
6.
I/O (A11)
59
6
98
95
134
F2
69
GND
-
137
F3
-
7.
I/O (A12)
60
7
99
96
138
E3
78
8.
I/O (A13)
61
8
100
97
139
C1
81
9.
I/O (A14)
62
9
1
98
142
B1
90
10.
I/O (A15)
63
10
2
99
143
B2
93
VCC
64
113100
144
C3
-
GND
-
12
4
1
C4
-
11.
GCK1 (A16, I/O)
1
13
5
2
B3
102
12.
I/O (A17)
2
14
6
3
A1
105
13.
I/O (TDI)
3
15
7
4
6
B4
111
14.
I/O (TCK)
4
16
8
5
7
A3
114
GND
-
8
C6
-
15.
I/O (TMS)
5
17
9
6
11
A5
117
16.
I/O
6
18
10
7
12
C7
123
17.
I/O
-
13
B7
126
18.
I/O
-
11
8
14
A6
129
19.
I/O
-
19
12
9
15
A7
135
20.
I/O
7
20
13
10
16
A8
138
GND
8
21
14
11
17
C8
-
VCC
9
22
15
12
18
B8
-
21.
I/O
-
23
16
13
19
C9
141
22.
I/O
10
24
17
14
20
B9
147
23.
I/O
-
18
15
21
A9
150
24.
I/O
-
22
B10
153
25.
I/O
-
25
19
16
23
C10
159
26.
I/O
11
26
20
17
24
A10
162
GND
-
27
C11
-
27.
I/O
12
27
21
18
28
B12
165
28.
I/O
-
22
19
29
A13
171
29.
I/O
13
28
23
20
32
B13
174
30.
I/O
14
29
24
21
33
B14
177
31.
M1 (I/O)
15
30
25
22
34
A15
186
GND
-
31
26
23
35
C13
-
32.
M0 (I/O)
16
32
27
24
36
A16
189
VCC
-
33
28
25
37
C14
-
33.
M2 (I/O)
17
34
29
26
38
B15
192
34.
GCK2 (I/O)
18
35
30
27
39
B16
195