1. At power-up, V
參數(shù)資料
型號: XC5206-5PC84C
廠商: Xilinx Inc
文件頁數(shù): 29/73頁
文件大?。?/td> 0K
描述: IC FPGA 196 CLB'S 84-PLCC
產(chǎn)品變化通告: XC5200 Discontinuation 27/Aug/2004
標準包裝: 15
系列: XC5200
LAB/CLB數(shù): 196
邏輯元件/單元數(shù): 784
輸入/輸出數(shù): 65
門數(shù): 10000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 84-LCC(J 形引線)
供應商設備封裝: 84-PLCC
其它名稱: 122-1138
R
November 5, 1998 (Version 5.2)
7-117
XC5200 Series Field Programmable Gate Arrays
7
.
Note:
1. At power-up, VCC must rise from 2.0 V to VCC min in less then 25 ms, otherwise delay configuration by pulling PROGRAM
Low until VCC is Valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 32: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2 TDRC
Address for Byte n + 1
D7
D6
A0-A17
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1 TRAC
7 CCLKs
CCLK
3 TRCD
Byte n - 1
X6078
Description
Symbol
Min
Max
Units
CCLK
Delay to Address valid
1
TRAC
0
200
ns
Data setup time
2
TDRC
60
ns
Data hold time
3
TRCD
0ns
Product Obsolete or Under Obsolescence
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