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參數(shù)資料
| 型號(hào)： | XC5202-6PQ100I |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（FPGA） |
| 文件頁數(shù)： | 49/73頁 |
| 文件大小： | 598K |
| 代理商： | XC5202-6PQ100I |
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R
November 5, 1998 (Version 5.2)
7-131
XC5200 Series Field Programmable Gate Arrays
7
XC5200 IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Speed Grade
-6
-5
-4
-3
Description
Symbol
Max
(ns)
Max
(ns)
Max
(ns)
Max
(ns)
Input
Propagation Delays from CMOS or TTL Levels
Pad to I (no delay)
Pad to I (with delay)
Output
Propagation Delays to CMOS or TTL Levels
Output (O) to Pad (fast)
Output (O) to Pad (slew-limited)
From clock (CK) to output pad (fast), using direct connect between Q
and output (O)
From clock (CK) to output pad (slew-limited), using direct connect be-
tween Q and output (O)
3-state to Pad active (fast)
3-state to Pad active (slew-limited)
Internal GTS to Pad active
T
PI
T
PID
5.7
11.4
5.0
10.2
4.8
10.2
3.3
9.5
T
OPF
T
OPS
T
OKPOF
4.6
9.5
10.1
4.5
8.4
9.3
4.5
8.0
8.3
3.5
5.0
7.5
T
OKPOS
14.9
13.1
11.8
10.0
T
TSONF
T
TSONS
T
GTS
5.6
10.4
17.7
5.2
9.0
15.9
4.9
8.3
14.7
4.6
6.0
13.5
Note:
1. Timing is measured at pin threshold, with 50-pF external capacitance loads.
Slew-limited
output rise/fall times are
approximately two times longer than
fast
output rise/fall times.
2. Unused and unbonded IOBs are configured by default as inputs with internal pull-up resistors.
3. Timing is based upon the XC5215 device. For other devices, see Timing Calculator.
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