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參數(shù)資料
| 型號： | XC5202-6PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 56/73頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 64 CLB'S 84-PLCC |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 系列： | XC5200 |
| LAB/CLB數(shù)： | 64 |
| 邏輯元件/單元數(shù)： | 256 |
| 輸入/輸出數(shù)： | 65 |
| 門數(shù)： | 3000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 84-PLCC |
| 其它名稱： | 122-1131 |
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R
XC5200 Series Field Programmable Gate Arrays
7-88
November 5, 1998 (Version 5.2)
Carry Function
The XC5200 family supports a carry-logic feature that
enhances the performance of arithmetic functions such as
counters, adders, etc. A carry multiplexer (CY_MUX) sym-
bol is used to indicate the XC5200 carry logic. This symbol
represents the dedicated 2:1 multiplexer in each LC that
performs the one-bit high-speed carry propagate per logic
cell (four bits per CLB).
While the carry propagate is performed inside the LC, an
adjacent LC must be used to complete the arithmetic func-
tion. Figure 6 represents an example of an adder function.
The carry propagate is performed on the CLB shown,
which also generates the half-sum for the four-bit adder. An
adjacent CLB is responsible for XORing the half-sum with
the corresponding carry-out. Thus an adder or counter
requires two LCs per bit. Notice that the carry chain
requires an initialization stage, which the XC5200 family
accomplishes using the carry initialize (CY_INIT) macro
and one additional LC. The carry chain can propagate ver-
tically up a column of CLBs.
The XC5200 library contains a set of Relationally-Placed
Macros (RPMs) and arithmetic functions designed to take
advantage of the dedicated carry logic. Using and modify-
ing these macros makes it much easier to implement cus-
Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
XOR
F=0
DI
FD
carry out
carry3
DO
D
X
LC3
DO
DQ
LC2
X
CI
carry in
CY_MUX
X
DO
LC1
LC0
CK
CE
CLR
D
Q
X
Q
half sum0
carry0
half sum2
half sum1
carry1
carry2
half sum3
CO
A3
or
B3
A3 and B3
to any two
A2 and B2
to any two
A2
or
B2
A1
or
B1
A1 and B1
to any two
A0
or
B0
A0 and B0
to any two
0
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
F4
F3
F2
F1
XOR
DI
FD
DO
FD
D
X
LC3
DO
DQ
LC2
X
CI
X
LC1
LC0
CK
CE
CLR
D
Q
X
Q
sum0
sum2
sum1
sum3
CO
Initialization of
carry chain (One Logic Cell)
X5709
Product Obsolete or Under Obsolescence
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