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    參數(shù)資料
    

    


    


    
型號(hào)：
XC4044XL-2HQ304C

    

    
廠商：
Xilinx Inc

    

    
文件頁(yè)數(shù)：
20/68頁(yè)

    

    
文件大?。?/td>
0K

    

    
描述：
IC FPGA C-TEMP 3.3V 2SPD 304HQFP

    

    
產(chǎn)品變化通告：
XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
    		

    

    
標(biāo)準(zhǔn)包裝：
12

    

    
系列：
XC4000E/X

    

    
LAB/CLB數(shù)：
1600
    		

    

    
邏輯元件/單元數(shù)：
3800
    		

    

    
RAM 位總計(jì)：
51200
    		

    

    
輸入/輸出數(shù)：
256
    		

    

    
門(mén)數(shù)：
44000
    		

    

    
電源電壓：
3 V ~ 3.6 V
    		

    

    
安裝類(lèi)型：
表面貼裝
    		

    

    
工作溫度：
0°C ~ 85°C
    		

    

    
封裝/外殼：
304-BFQFP 裸露焊盤(pán)
    		

    

    
供應(yīng)商設(shè)備封裝：
304-PQFP（40x40）
    		

    

    

    

	
    
    
    

    
    
	
    R
    May 14, 1999 (Version 1.6)
    6-31
    XC4000E and XC4000X Series Field Programmable Gate Arrays
    6
    Double-Length Lines
    The double-length lines consist of a grid of metal segments,
    each twice as long as the single-length lines: they run past
    two CLBs before entering a switch matrix. Double-length
    lines are grouped in pairs with the switch matrices stag-
    gered, so that each line goes through a switch matrix at
    every other row or column of CLBs (see Figure 28).
    There are four vertical and four horizontal double-length
    lines associated with each CLB. These lines provide faster
    signal routing over intermediate distances, while retaining
    routing exibility. Double-length lines are connected by way
    of the programmable switch matrices. Routing connectivity
    is shown in Figure 27.
    Quad Lines (XC4000X only)
    XC4000X devices also include twelve vertical and twelve
    horizontal quad lines per CLB row and column. Quad lines
    are four times as long as the single-length lines. They are
    interconnected via buffered switch matrices (shown as dia-
    monds in Figure 27 on page 30). Quad lines run past four
    CLBs before entering a buffered switch matrix. They are
    grouped in fours, with the buffered switch matrices stag-
    gered, so that each line goes through a buffered switch
    matrix at every fourth CLB location in that row or column.
    The buffered switch matrixes have four pins, one on each
    edge. All of the pins are bidirectional. Any pin can drive any
    or all of the other pins.
    Each buffered switch matrix contains one buffer and six
    pass transistors. It resembles the programmable switch
    matrix shown in Figure 26, with the addition of a program-
    mable buffer. There can be up to two independent inputs
    and up to two independent outputs. Only one of the inde-
    pendent inputs can be buffered.
    The place and route software automatically uses the timing
    requirements of the design to determine whether or not a
    quad line signal should be buffered. A heavily loaded signal
    is typically buffered, while a lightly loaded one is not. One
    scenario is to alternate buffers and pass transistors. This
    allows both vertical and horizontal quad lines to be buffered
    at alternating buffered switch matrices.
    Due to the buffered switch matrices, quad lines are very
    fast. They provide the fastest available method of routing
    heavily loaded signals for long distances across the device.
    Longlines
    Longlines form a grid of metal interconnect segments that
    run the entire length or width of the array. Longlines are
    intended for high fan-out, time-critical signal nets, or nets
    that are distributed over long distances. In XC4000X
    devices, quad lines are preferred for critical nets, because
    the buffered switch matrices make them faster for high
    fan-out nets.
    Two horizontal longlines per CLB can be driven by 3-state
    or open-drain drivers (TBUFs). They can therefore imple-
    ment unidirectional or bidirectional buses, wide multiplex-
    ers, or wired-AND functions. (See “Three-State Buffers” on
    page 26 for more details.)
    Each horizontal longline driven by TBUFs has either two
    (XC4000E) or eight (XC4000X) pull-up resistors. To acti-
    vate these resistors, attach a PULLUP symbol to the
    long-line net. The software automatically activates the
    appropriate number of pull-ups. There is also a weak
    keeper at each end of these two horizontal longlines. This
    CLB
    PSM
    CLB
    Doubles
    Singles
    Doubles
    X6601
    Figure 28: Single- and Double-Length Lines, with
    Programmable Switch Matrices (PSMs)
    CLB
    X9014
    Figure 29: Quad Lines (XC4000X only)
    Product Obsolete or Under Obsolescence
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XC4044XL-2HQ304I
功能描述:IC FPGA I-TEMP 3.3V 2SPD 304HQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

    

    
XC4044XL3BG352C
 制造商:Xilinx 功能描述:

    

    
XC4044XL-3BG352C
功能描述:IC FPGA C-TEMP 3.3V 3SPD 352MBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

    

    
XC4044XL-3BG352I
功能描述:IC FPGA I-TEMP 3.3V 3SPD 352MBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

    

    
XC4044XL-3BG432C
功能描述:IC FPGA C-TEMP 3.3V 3SPD 432MBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

    

    
    
    
    
	
    	
    
    
     
     
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