• <span id="25rs7"><pre id="25rs7"></pre></span>
      參數(shù)資料
      型號(hào): XC4036XL-3HQ240C
      廠商: Xilinx Inc
      文件頁(yè)數(shù): 18/68頁(yè)
      文件大小: 0K
      描述: IC FPGA C-TEMP 3.3V 3SPD 240HQFP
      產(chǎn)品變化通告: XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
      標(biāo)準(zhǔn)包裝: 24
      系列: XC4000E/X
      LAB/CLB數(shù): 1296
      邏輯元件/單元數(shù): 3078
      RAM 位總計(jì): 41472
      輸入/輸出數(shù): 193
      門數(shù): 36000
      電源電壓: 3 V ~ 3.6 V
      安裝類型: 表面貼裝
      工作溫度: 0°C ~ 85°C
      封裝/外殼: 240-BFQFP 裸露焊盤
      供應(yīng)商設(shè)備封裝: 240-PQFP(32x32)
      R
      May 14, 1999 (Version 1.6)
      6-29
      XC4000E and XC4000X Series Field Programmable Gate Arrays
      6
      Table 14: Routing per CLB in XC4000 Series Devices
      Programmable Switch Matrices
      The horizontal and vertical single- and double-length lines
      intersect at a box called a programmable switch matrix
      (PSM). Each switch matrix consists of programmable pass
      transistors used to establish connections between the lines
      For example, a single-length signal entering on the right
      side of the switch matrix can be routed to a single-length
      line on the top, left, or bottom sides, or any combination
      thereof, if multiple branches are required. Similarly, a dou-
      ble-length signal can be routed to a double-length line on
      any or all of the other three edges of the programmable
      switch matrix.
      Single-Length Lines
      Single-length lines provide the greatest interconnect exi-
      bility and offer fast routing between adjacent blocks. There
      are eight vertical and eight horizontal single-length lines
      associated with each CLB. These lines connect the switch-
      ing matrices that are located in every row and a column of
      CLBs.
      Single-length lines are connected by way of the program-
      mable switch matrices, as shown in Figure 28. Routing
      connectivity is shown in Figure 27.
      Single-length lines incur a delay whenever they go through
      a switching matrix. Therefore, they are not suitable for rout-
      ing signals for long distances. They are normally used to
      conduct signals within a localized area and to provide the
      branching for nets with fanout greater than one.
      x5994
      Quad
      Single
      Double
      Long
      Direct
      Connect
      Long
      CLB
      Long
      Global
      Clock
      Long
      Double Single
      Global
      Clock
      Carry
      Chain
      Direct
      Connect
      Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
      XC4000E
      XC4000X
      Vertical Horizontal Vertical Horizontal
      Singles
      8
      Doubles
      4
      Quads
      0
      12
      Longlines
      6
      10
      6
      Direct
      Connects
      00
      2
      Globals
      4
      0
      8
      0
      Carry Logic
      2
      0
      1
      0
      Total
      24
      18
      45
      32
      Six Pass Transistors
      Per Switch Matrix
      Interconnect Point
      Singles
      Double
      Singles
      Double
      X6600
      Figure 26: Programmable Switch Matrix (PSM)
      Product Obsolete or Under Obsolescence
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