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      參數(shù)資料
      

      


      


      
型號(hào)：
XC4025E-4HQ240C

      

      
廠商：
Xilinx Inc

      

      
文件頁(yè)數(shù)：
14/68頁(yè)

      

      
文件大小：
0K

      

      
描述：
IC FPGA C-TEMP 5V 4 SPD 240-HQFP

      

      
產(chǎn)品變化通告：
XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
      		

      

      
標(biāo)準(zhǔn)包裝：
24

      

      
系列：
XC4000E/X

      

      
LAB/CLB數(shù)：
1024
      		

      

      
邏輯元件/單元數(shù)：
2432
      		

      

      
RAM 位總計(jì)：
32768
      		

      

      
輸入/輸出數(shù)：
193
      		

      

      
門數(shù)：
25000
      		

      

      
電源電壓：
4.75 V ~ 5.25 V
      		

      

      
安裝類型：
表面貼裝
      		

      

      
工作溫度：
0°C ~ 85°C
      		

      

      
封裝/外殼：
240-BFQFP 裸露焊盤
      		

      

      
供應(yīng)商設(shè)備封裝：
240-PQFP（32x32）
      		

      

      

      

	
      
    
    

    
      
	
      R
      May 14, 1999 (Version 1.6)
      6-25
      XC4000E and XC4000X Series Field Programmable Gate Arrays
      6
      Output Multiplexer/2-Input Function Generator
      (XC4000X only)
      As shown in Figure 16 on page 21, the output path in the
      XC4000X IOB contains an additional multiplexer not avail-
      able in the XC4000E IOB. The multiplexer can also be con-
      gured as a 2-input function generator, implementing a
      pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2
      inverted inputs. The logic used to implement these func-
      tions is shown in the upper gray area of Figure 16.
      When congured as a multiplexer, this feature allows two
      output signals to time-share the same output pad; effec-
      tively doubling the number of device outputs without requir-
      ing a larger, more expensive package.
      When the MUX is congured as a 2-input function genera-
      tor, logic can be implemented within the IOB itself. Com-
      bined with a Global Early buffer, this arrangement allows
      very high-speed gating of a single signal. For example, a
      wide decoder can be implemented in CLBs, and its output
      gated with a Read or Write Strobe Driven by a BUFGE
      buffer, as shown in Figure 19. The critical-path pin-to-pin
      delay of this circuit is less than 6 nanoseconds.
      As shown in Figure 16, the IOB input pins Out, Output
      Clock, and Clock Enable have different delays and different
      exibilities regarding polarity. Additionally, Output Clock
      sources are more limited than the other inputs. Therefore,
      the Xilinx software does not move logic into the IOB func-
      tion generators unless explicitly directed to do so.
      The user can specify that the IOB function generator be
      used, by placing special library symbols beginning with the
      letter “O.” For example, a 2-input AND-gate in the IOB func-
      tion generator is called OAND2. Use the symbol input pin
      labelled “F” for the signal on the critical path. This signal is
      placed on the OK pin — the IOB input with the shortest
      delay to the function generator. Two examples are shown in
      Other IOB Options
      There are a number of other programmable options in the
      XC4000 Series IOB.
      Pull-up and Pull-down Resistors
      Programmable pull-up and pull-down resistors are useful
      for tying unused pins to Vcc or Ground to minimize power
      consumption and reduce noise sensitivity. The congurable
      pull-up resistor is a p-channel transistor that pulls to Vcc.
      The congurable pull-down resistor is an n-channel transis-
      tor that pulls to Ground.
      The value of these resistors is 50 k
       100 k. This high
      value makes them unsuitable as wired-AND pull-up resis-
      tors.
      The pull-up resistors for most user-programmable IOBs are
      active during the conguration process. See Table 22 on
      page 58 for a list of pins with pull-ups active before and dur-
      ing conguration.
      After conguration, voltage levels of unused pads, bonded
      or un-bonded, must be valid logic levels, to reduce noise
      sensitivity and avoid excess current. Therefore, by default,
      unused pads are congured with the internal pull-up resis-
      tor active. Alternatively, they can be individually congured
      with the pull-down resistor, or as a driven output, or to be
      driven by an external source. To activate the internal
      pull-up, attach the PULLUP library component to the net
      attached to the pad. To activate the internal pull-down,
      attach the PULLDOWN library component to the net
      attached to the pad.
      Independent Clocks
      Separate clock signals are provided for the input and output
      ip-ops. The clock can be independently inverted for each
      ip-op within the IOB, generating either falling-edge or ris-
      ing-edge triggered ip-ops. The clock inputs for each IOB
      are independent, except that in the XC4000X, the Fast
      Capture latch shares an IOB input with the output clock pin.
      Early Clock for IOBs (XC4000X only)
      Special early clocks are available for IOBs. These clocks
      are sourced by the same sources as the Global Low-Skew
      buffers, but are separately buffered. They have fewer loads
      and therefore less delay. The early clock can drive either
      the IOB output clock or the IOB input clock, or both. The
      early clock allows fast capture of input data, and fast
      clock-to-output on output data. The Global Early buffers
      that drive these clocks are described in “Global Nets and
      Global Set/Reset
      As with the CLB registers, the Global Set/Reset signal
      (GSR) can be used to set or clear the input and output reg-
      isters, depending on the value of the INIT attribute or prop-
      erty. The two ip-ops can be individually congured to set
      IPAD
      F
      OPAD
      FAST
      BUFGE
      OAND2
      from
      internal
      logic
      X9019
      Figure 19: Fast Pin-to-Pin Path in XC4000X
      OAND2
      F
      X6598
      D0
      S0
      D1
      O
      OMUX2
      X6599
      Figure 20: AND & MUX Symbols in XC4000X IOB
      Product Obsolete or Under Obsolescence
      
    
      
    
    
      


      


      

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      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
XC4025E-4HQ240I
功能描述:IC FPGA I-TEMP 5V 4 SPD 240-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4025E-4HQ304C
功能描述:IC FPGA C-TEMP 5V 4 SPD 304-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4025E-4HQ304I
功能描述:IC FPGA I-TEMP 5V 4 SPD 304-HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4025E-4PG223C
功能描述:IC FPGA C-TEMP 5V 4 SPD 223-CPGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4025E-4PG223I
功能描述:IC FPGA I-TEMP 5V 4 SPD 223-CPGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
    
    
    
	
      	
    
    
     
     
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