參數(shù)資料
型號： XC4020XL-3HT176I
廠商： Xilinx Inc
文件頁數(shù)： 59/68頁
文件大?。?/td> 0K
描述： IC FPGA I 3.3V 3SPD 176HTQFP
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標準包裝： 40
系列： XC4000E/X
LAB/CLB數(shù)： 784
邏輯元件/單元數(shù)： 1862
RAM 位總計： 25088
輸入/輸出數(shù)： 145
門數(shù)： 20000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 176-LQFP 裸露焊盤
供應商設備封裝： 176-TQFP（24x24）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-66
May 14, 1999 (Version 1.6)
Asynchronous Peripheral Mode
Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of WS and CS0 being Low and RS
and CS1 being High to accept byte-wide data from a micro-
processor bus. In the lead FPGA, this data is loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic.
The lead FPGA presents the preamble data (and all data
that overows the lead device) on its DOUT pin. The
RDY/BUSY output from the lead FPGA acts as a hand-
shake signal to the microprocessor. RDY/BUSY goes Low
when a byte has been received, and goes High again when
the byte-wide input buffer has transferred its information
into the shift register, and the buffer is ready to receive new
data. A new write may be started immediately, as soon as
the RDY/BUSY output has gone Low, acknowledging
receipt of the previous data. Write may not be terminated
until RDY/BUSY is High again for one CCLK period. Note
that RDY/BUSY is pulled High with a high-impedance
pull-up prior to INIT going High.
The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new byte
was received, the BUSY signal lasts for only two CCLK
periods. If the shift register was still full when the new byte
was received, the BUSY signal can be as long as nine
CCLK periods.
Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
The READY/BUSY handshake can be ignored if the delay
from any one Write to the end of the next Write is guaran-
teed to be longer than 10 CCLK periods.
Status Read
The logic AND condition of the CS0, CS1and RS inputs
puts the device status on the Data bus.
D7 High indicates Ready
D7 Low indicates Busy
D0 through D6 go unconditionally High
It is mandatory that the whole start-up sequence be started
and completed by one byte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and interfere with the nal byte transfer. If this
transfer does not occur, the start-up sequence is not com-
pleted all the way to the nish (point F in Figure 47 on page
In this case, at worst, the internal reset is not released. At
best, Readback and Boundary Scan are inhibited. The
length-count value, as generated by the XACT
step soft-
ware, ensures that these problems never occur.
Although RDY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, D7 represents the
RDY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.
Asynchronous Peripheral mode is selected by a <101> on
the mode pins (M2, M1, M0).
ADDRESS
BUS
DATA
BUS
ADDRESS
DECODE
LOGIC
CS0
...
RDY/BUSY
WS
PROGRAM
D0–7
CCLK
DOUT
DIN
M2
M0
M1
N/C
RS
CS1
CONTROL
SIGNALS
INIT
REPROGRAM
OPTIONAL
DAISY-CHAINED
FPGAs
VCC
DONE
8
X9028
4.7 k
4.7 k
4.7 k
4.7 k
XC4000E/X
ASYNCHRO-
NOUS
PERIPHERAL
PROGRAM
CCLK
DOUT
M2
M0
M1
INIT
DONE
XC4000E/X
SLAVE
Figure 58:
Asynchronous Peripheral Mode Circuit Diagram
Product Obsolete or Under Obsolescence
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