參數(shù)資料
型號(hào)： XC4020E-4HQ240I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 54/68頁(yè)
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 5V 4SPD 240-HQFP
產(chǎn)品變化通告： XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010
標(biāo)準(zhǔn)包裝： 24
系列： XC4000E/X
LAB/CLB數(shù)： 784
邏輯元件/單元數(shù)： 1862
RAM 位總計(jì)： 25088
輸入/輸出數(shù)： 193
門數(shù)： 20000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 240-PQFP（32x32）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-62
May 14, 1999 (Version 1.6)
Master Parallel Modes
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decre-
menting the address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data—and all data that over-
ows the lead device—on its DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CCLK edge.
The PROM address pins can be incremented or decre-
mented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and micro controllers. Some processors
must boot from the bottom of memory (all zeros) while oth-
ers must boot from the top. The FPGA is exible and can
load its conguration bitstream from either end of the mem-
ory.
Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, M0). The EPROM addresses start at
00000 and increment.
Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.
Additional Address lines in XC4000 devices
The XC4000X devices have additional address lines
(A18-A21) allowing the additional address space required
to daisy-chain several large devices.
The extra address lines are programmable in XC4000EX
devices. By default these address lines are not activated. In
the default mode, the devices are compatible with existing
XC4000 and XC4000E products. If desired, the extra
address lines can be used by specifying the address lines
option in bitgen as 22 (bitgen -g AddressLines:22). The
lines (A18-A21) are driven when a master device detects,
via the bitstream, that it should be using all 22 address
lines. Because these pins will initially be pulled high by
internal pull-ups, designers using Master Parallel Up mode
should use external pull down resistors on pins A18-A21. If
Master Parallel Down mode is used external resistors are
not necessary.
All 22 address lines are always active in Master Parallel
modes with XC4000XL devices. The additional address
lines behave identically to the lower order address lines. If
the Address Lines option in bitgen is set to 18, it will be
ignored by the XC4000XL device.
The additional address lines (A18-A21) are not available in
the PC84 package.
M0
M1
DOUT
VCC
M2
PROGRAM
D7
D6
D5
D4
D3
D2
D1
D0
PROGRAM
CCLK
DIN
M0
M1
M2
DOUT
PROGRAM
EPROM
(8K x 8)
(OR LARGER)
A10
A11
A12
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
DONE
D6
D5
D4
D3
D2
D1
D0
N/C
CE
OE
XC4000E/X
SLAVE
8
DATA BUS
CCLK
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
INIT
. . .
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BETWEEN
ALTERNATIVE CONFIGURATIONS
DONE
TO DIN OF OPTIONAL
DAISY-CHAINED FPGAS
A16
. . .
A17
. . .
HIGH
or
LOW
X9026
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS
4.7K
4.7K
NOTE:M0 can be shorted
to Ground if not used
as I/O.
Figure 54: Master Parallel Mode Circuit Diagram
Product Obsolete or Under Obsolescence
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