參數(shù)資料
型號(hào): XC4020E-2PG223I
廠商: Xilinx Inc
文件頁(yè)數(shù): 49/68頁(yè)
文件大?。?/td> 0K
描述: IC FPGA I-TEMP 5V 2SPD 223-CPGA
產(chǎn)品變化通告: XC4000(E,L) Discontinuation 01/April/2002
標(biāo)準(zhǔn)包裝: 12
系列: XC4000E/X
LAB/CLB數(shù): 784
邏輯元件/單元數(shù): 1862
RAM 位總計(jì): 25088
輸入/輸出數(shù): 192
門(mén)數(shù): 20000
電源電壓: 4.5 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 223-BCBGA
供應(yīng)商設(shè)備封裝: 223-CPGA(47.25x47.25)
R
May 14, 1999 (Version 1.6)
6-57
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E/EX/XL Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reect worst-case values over the recommended operating conditions.
Note 1:
Timing parameters apply to all speed grades.
Note 2:
If rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback.
Note 1:
Timing parameters apply to all speed grades.
Note 2:
If rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback.
RTRC
T
RCRT
T
RCRT
T
2
RCL
T
4
RCRR
T
6
RCH
T
5
RCRD
T
7
DUMMY
rdbk.DATA
rdbk.RIP
rdclk.I
rdbk.TRIG
Finished
Internal Net
VALID
X1790
VALID
1
RTRC
T
1
E/EX
Description
Symbol
Min
Max
Units
rdbk.TRIG
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
1
2
TRTRC
TRCRT
200
50
-
ns
rdclk.1
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
7
6
5
4
TRCRD
TRCRR
TRCH
TRCL
-
250
500
ns
XL
Description
Symbol
Min
Max
Units
rdbk.TRIG
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
1
2
TRTRC
TRCRT
200
50
-
ns
rdclk.1
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
7
6
5
4
TRCRD
TRCRR
TRCH
TRCL
-
250
500
ns
Product Obsolete or Under Obsolescence
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