• 參數(shù)資料
    型號(hào): XC4013E-3BG225I
    廠商: Xilinx Inc
    文件頁數(shù): 12/68頁
    文件大?。?/td> 0K
    描述: IC FPGA I-TEMP 5V 3SPD 225-PBGA
    產(chǎn)品變化通告: Product Discontinuation 28/Jul/2010
    標(biāo)準(zhǔn)包裝: 40
    系列: XC4000E/X
    LAB/CLB數(shù): 576
    邏輯元件/單元數(shù): 1368
    RAM 位總計(jì): 18432
    輸入/輸出數(shù): 192
    門數(shù): 13000
    電源電壓: 4.5 V ~ 5.5 V
    安裝類型: 表面貼裝
    工作溫度: -40°C ~ 100°C
    封裝/外殼: 225-BBGA
    供應(yīng)商設(shè)備封裝: 225-PBGA
    R
    May 14, 1999 (Version 1.6)
    6-7
    XC4000E and XC4000X Series Field Programmable Gate Arrays
    6
    XC4000E and XC4000X Series
    Compared to the XC4000
    For readers already familiar with the XC4000 family of Xil-
    inx Field Programmable Gate Arrays, the major new fea-
    tures in the XC4000 Series devices are listed in this
    section. The
    biggest
    advantages
    of
    XC4000E
    and
    XC4000X devices are signicantly increased system
    speed, greater capacity, and new architectural features,
    particularly Select-RAM memory.
    The XC4000X devices
    also offer many new routing features, including special
    high-speed clock buffers that can be used to capture input
    data with minimal delay.
    Any XC4000E device is pinout- and bitstream-compatible
    with the corresponding XC4000 device. An existing
    XC4000 bitstream can be used to program an XC4000E
    device. However, since the XC4000E includes many new
    features, an XC4000E bitstream cannot be loaded into an
    XC4000 device.
    XC4000X Series devices are not bitstream-compatible with
    equivalent array size devices in the XC4000 or XC4000E
    families. However, equivalent array size devices, such as
    the XC4025, XC4025E, XC4028EX, and XC4028XL, are
    pinout-compatible.
    Improvements in XC4000E and XC4000X
    Increased System Speed
    XC4000E and XC4000X devices can run at synchronous
    system clock rates of up to 80 MHz, and internal perfor-
    mance can exceed 150 MHz. This increase in performance
    over the previous families stems from improvements in both
    device processing and system architecture.
    XC4000
    Series devices use a sub-micron multi-layer metal process.
    In addition, many architectural improvements have been
    made, as described below.
    The XC4000XL family is a high performance 3.3V family
    based on 0.35
    SRAM technology and supports system
    speeds to 80 MHz.
    PCI Compliance
    XC4000 Series -2 and faster speed grades are fully PCI
    compliant. XC4000E and XC4000X devices can be used to
    implement a one-chip PCI solution.
    Carry Logic
    The speed of the carry logic chain has increased dramati-
    cally. Some parameters, such as the delay on the carry
    chain through a single CLB (TBYP), have improved by as
    much as 50% from XC4000 values. See “Fast Carry Logic”
    on page 18 for more information.
    Select-RAM Memory: Edge-Triggered, Synchro-
    nous RAM Modes
    The RAM in any CLB can be congured for synchronous,
    edge-triggered, write operation. The read operation is not
    affected by this change to an edge-triggered write.
    Dual-Port RAM
    A separate option converts the 16x2 RAM in any CLB into a
    16x1 dual-port RAM with simultaneous Read/Write.
    The function generators in each CLB can be congured as
    either level-sensitive (asynchronous) single-port RAM,
    edge-triggered (synchronous) single-port RAM, edge-trig-
    gered (synchronous) dual-port RAM, or as combinatorial
    logic.
    Congurable RAM Content
    The RAM content can now be loaded at conguration time,
    so that the RAM starts up with user-dened data.
    H Function Generator
    In current XC4000 Series devices, the H function generator
    is more versatile than in the original XC4000. Its inputs can
    come not only from the F and G function generators but
    also from up to three of the four control input lines. The H
    function generator can thus be totally or partially indepen-
    dent of the other two function generators, increasing the
    maximum capacity of the device.
    IOB Clock Enable
    The two ip-ops in each IOB have a common clock enable
    input, which through conguration can be activated individ-
    ually for the input or output ip-op or both. This clock
    enable operates exactly like the EC pin on the XC4000
    CLB. This new feature makes the IOBs more versatile, and
    avoids the need for clock gating.
    Output Drivers
    The output pull-up structure defaults to a TTL-like
    totem-pole. This driver is an n-channel pull-up transistor,
    pulling to a voltage one transistor threshold below Vcc, just
    like the XC4000 family outputs. Alternatively, XC4000
    Series devices can be globally congured with CMOS out-
    puts, with p-channel pull-up transistors pulling to Vcc. Also,
    the congurable pull-up resistor in the XC4000 Series is a
    p-channel transistor that pulls to Vcc, whereas in the origi-
    nal XC4000 family it is an n-channel transistor that pulls to
    a voltage one transistor threshold below Vcc.
    Product Obsolete or Under Obsolescence
    相關(guān)PDF資料
    PDF描述
    XC4013E-3BG225C IC FPGA C-TEMP 5V 3SPD 225-PBGA
    AMC60DRYH-S13 CONN EDGECARD 120POS .100 EXTEND
    FB8S029JA1 CONN FFC/FPC 0.3MM 29POS R/A SMD
    ACB108DHBT CONN EDGECARD 216PS R/A .050 DIP
    ABB105DHBR CONN EDGECARD 210PS R/A .050 SLD
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    XC4013E-3BG225I0167 制造商:Xilinx 功能描述:
    XC4013E-3BG240C 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
    XC4013E-3BG240I 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
    XC4013E-3BG240M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
    XC4013E-3CB240C 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays