參數(shù)資料
    

    


    


    
型號(hào)：
XC4010E-2HQ208I

    

    
廠商：
Xilinx Inc

    

    
文件頁(yè)數(shù)：
15/68頁(yè)

    

    
文件大小：
0K

    

    
描述：
IC FPGA I-TEMP 5V 2SPD 208-HQFP

    

    
產(chǎn)品變化通告：
XC4000(XL,XLA,E) Discontinuation 15/Nov/2004
    		

    

    
標(biāo)準(zhǔn)包裝：
24

    

    
系列：
XC4000E/X

    

    
LAB/CLB數(shù)：
400
    		

    

    
邏輯元件/單元數(shù)：
950
    		

    

    
RAM 位總計(jì)：
12800
    		

    

    
輸入/輸出數(shù)：
160
    		

    

    
門(mén)數(shù)：
10000
    		

    

    
電源電壓：
4.5 V ~ 5.5 V
    		

    

    
安裝類(lèi)型：
表面貼裝
    		

    

    
工作溫度：
-40°C ~ 100°C
    		

    

    
封裝/外殼：
208-BFQFP 裸露焊盤(pán)
    		

    

    
供應(yīng)商設(shè)備封裝：
208-PQFP（28x28）
    		

    

    

    

	
    
    
    

    
    
	
    R
    XC4000E and XC4000X Series Field Programmable Gate Arrays
    6-26
    May 14, 1999 (Version 1.6)
    or clear on reset and after conguration. Other than the glo-
    bal GSR net, no user-controlled set/reset signal is available
    to the I/O ip-ops. The choice of set or clear applies to
    both the initial state of the ip-op and the response to the
    Global Set/Reset pulse. See “Global Set/Reset” on
    page 11 for a description of how to use GSR.
    JTAG Support
    Embedded logic attached to the IOBs contains test struc-
    tures compatible with IEEE Standard 1149.1 for boundary
    scan testing, permitting easy chip and board-level testing.
    More information is provided in “Boundary Scan” on
    Three-State Buffers
    A pair of 3-state buffers is associated with each CLB in the
    array. (See Figure 27 on page 30.) These 3-state buffers
    can be used to drive signals onto the nearest horizontal
    longlines above and below the CLB. They can therefore be
    used to implement multiplexed or bidirectional buses on the
    horizontal longlines, saving logic resources. Programmable
    pull-up resistors attached to these longlines help to imple-
    ment a wide wired-AND function.
    The buffer enable is an active-High 3-state (i.e. an
    active-Low enable), as shown in Table 13.
    Another 3-state buffer with similar access is located near
    each I/O block along the right and left edges of the array.
    The horizontal longlines driven by the 3-state buffers have
    a weak keeper at each end. This circuit prevents undened
    oating levels. However, it is overridden by any driver, even
    a pull-up resistor.
    Special longlines running along the perimeter of the array
    can be used to wire-AND signals coming from nearby IOBs
    or from internal longlines. These longlines form the wide
    edge decoders discussed in “Wide Edge Decoders” on
    Three-State Buffer Modes
    The 3-state buffers can be congured in three modes:
    Standard 3-state buffer
    Wired-AND with input on the I pin
    Wired OR-AND
    Standard 3-State Buffer
    All three pins are used. Place the library element BUFT.
    Connect the input to the I pin and the output to the O pin.
    The T pin is an active-High 3-state (i.e. an active-Low
    enable). Tie the T pin to Ground to implement a standard
    buffer.
    Wired-AND with Input on the I Pin
    The buffer can be used as a Wired-AND. Use the WAND1
    library symbol, which is essentially an open-drain buffer.
    WAND4, WAND8, and WAND16 are also available. See the
    XACT Libraries Guide for further information.
    The T pin is internally tied to the I pin. Connect the input to
    the I pin and the output to the O pin. Connect the outputs of
    all the WAND1s together and attach a PULLUP symbol.
    Wired OR-AND
    The buffer can be congured as a Wired OR-AND. A High
    level on either input turns off the output. Use the
    WOR2AND library symbol, which is essentially an
    open-drain 2-input OR gate. The two input pins are func-
    tionally equivalent. Attach the two inputs to the I0 and I1
    pins and tie the output to the O pin. Tie the outputs of all the
    WOR2ANDs together and attach a PULLUP symbol.
    Three-State Buffer Examples
    Figure 21 shows how to use the 3-state buffers to imple-
    ment a wired-AND function. When all the buffer inputs are
    High, the pull-up resistor(s) provide the High output.
    Figure 22 shows how to use the 3-state buffers to imple-
    ment a multiplexer. The selection is accomplished by the
    buffer 3-state signal.
    Pay particular attention to the polarity of the T pin when
    using these buffers in a design. Active-High 3-state (T) is
    identical to an active-Low output enable, as shown in
    Table 13: Three-State Buffer Functionality
    IN
    T
    OUT
    X1
    Z
    IN
    0
    IN
    P
    U
    L
    U
    P
    Z = D
    A
    q
    D
    B
    q
    (D
    C
    +D
    D
    ) q (D
    E
    +D
    F
    )
    D
    E
    D
    F
    D
    C
    D
    B
    D
    A
    WAND1
    WOR2AND
    X6465
    Figure 21: Open-Drain Buffers Implement a Wired-AND Function
    Product Obsolete or Under Obsolescence
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
XC4010E-2HQ208C
IC FPGA C-TEMP 5V 2SPD 208-HQFP

    

    
XC4010E-2BG225I
IC FPGA I-TEMP 5V 2SPD 225-PBGA

    

    
88637-3
016 HOUSING FFC RCPT DR 100CL

    

    
6-487937-0
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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XC4010E-2PC84C
功能描述:IC FPGA C-TEMP 5V 2SPD 84-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789

    

    
XC4010E-2PC84I
功能描述:IC FPGA I-TEMP 5V 2SPD 84-PLCC RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789

    

    
XC4010E-2PG191C
功能描述:IC FPGA C-TEMP 5V 2SPD 191-CPGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789

    

    
XC4010E-2PG191I
功能描述:IC FPGA I-TEMP 5V 2SPD 191-CPGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789

    

    
XC4010E-2PQ160C
功能描述:IC FPGA C-TEMP 5V 2SPD 160-PQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門(mén)數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱(chēng):122-1789

    

    
    
    
    
	
    	
    
    
     
     
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