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  • 參數(shù)資料
    型號: XC4006E-2PQ160I
    廠商: Xilinx Inc
    文件頁數(shù): 47/68頁
    文件大?。?/td> 0K
    描述: IC FPGA I-TEMP 5V 2SPD 160-PQFP
    產(chǎn)品變化通告: XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
    標(biāo)準(zhǔn)包裝: 1
    系列: XC4000E/X
    LAB/CLB數(shù): 256
    邏輯元件/單元數(shù): 608
    RAM 位總計: 8192
    輸入/輸出數(shù): 128
    門數(shù): 6000
    電源電壓: 4.5 V ~ 5.5 V
    安裝類型: 表面貼裝
    工作溫度: -40°C ~ 100°C
    封裝/外殼: 160-BQFP
    供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
    R
    May 14, 1999 (Version 1.6)
    6-55
    XC4000E and XC4000X Series Field Programmable Gate Arrays
    6
    Readback
    The user can read back the content of conguration mem-
    ory and the level of certain internal nodes without interfer-
    ing with the normal operation of the device.
    Readback not only reports the downloaded conguration
    bits, but can also include the present state of the device,
    represented by the content of all ip-ops and latches in
    CLBs and IOBs, as well as the content of function genera-
    tors used as RAMs.
    Note that in XC4000 Series devices, conguration data is
    not inverted with respect to conguration as it is in XC2000
    and XC3000 families.
    XC4000 Series Readback does not use any dedicated
    pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
    RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
    To access the internal Readback signals, place the READ-
    BACK library symbol and attach the appropriate pad sym-
    bols, as shown in Figure 49.
    After Readback has been initiated by a High level on
    RDBK.TRIG after conguration, the RDBK.RIP (Read In
    Progress) output goes High on the next rising edge of
    RDBK.CLK. Subsequent rising edges of this clock shift out
    Readback data on the RDBK.DATA net.
    Readback data does not include the preamble, but starts
    with ve dummy bits (all High) followed by the Start bit
    (Low) of the rst frame. The rst two data bits of the rst
    frame are always High.
    Each frame ends with four error check bits. They are read
    back as High. The last seven bits of the last frame are also
    read back as High. An additional Start bit (Low) and an
    11-bit Cyclic Redundancy Check (CRC) signature follow,
    before RDBK.RIP returns Low.
    DONE
    *
    **
    QS
    R
    1
    0
    1
    0
    1
    0
    1
    0
    1
    GSR ENABLE
    GSR INVERT
    STARTUP.GSR
    STARTUP.GTS
    GTS INVERT
    GTS ENABLE
    CONTROLLED BY STARTUP SYMBOL
    IN THE USER SCHEMATIC (SEE
    LIBRARIES GUIDE)
    GLOBAL SET/RESET OF
    ALL CLB AND IOB FLIP-FLOP
    IOBs OPERATIONAL PER CONFIGURATION
    GLOBAL 3-STATE OF ALL IOBs
    Q2
    Q3
    Q1/Q4
    DONE
    IN
    STARTUP
    Q0
    Q1
    Q2
    Q3
    Q4
    M
    " FINISHED "
    ENABLES BOUNDARY
    SCAN, READBACK AND
    CONTROLS THE OSCILLATOR
    K
    SQ
    K
    DQ
    K
    DQ
    K
    DQ
    K
    DQ
    FULL
    LENGTH COUNT
    CLEAR MEMORY
    CCLK
    STARTUP.CLK
    USER NET
    CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
    X1528
    Figure 48: Start-up Logic
    Product Obsolete or Under Obsolescence
    相關(guān)PDF資料
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