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參數(shù)資料
| 型號： | XC4005XL-3TQ144I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 8/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA I-TEMP 3.3V 3SPD 144TQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 27/Apr/2010 |
| 標準包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 196 |
| 邏輯元件/單元數(shù)： | 466 |
| RAM 位總計： | 6272 |
| 輸入/輸出數(shù)： | 112 |
| 門數(shù)： | 5000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-20
May 14, 1999 (Version 1.6)
Input/Output Blocks (IOBs)
User-congurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
gured for input, output, or bidirectional signals.
Figure 15 shows a simplied block diagram of the
XC4000E IOB. A more complete diagram which includes
the boundary scan logic of the XC4000E IOB can be found
in Figure 40 on page 43, in the “Boundary Scan” section.
The XC4000X IOB contains some special features not
included in the XC4000E IOB. These features are high-
lighted in a simplied block diagram found in Figure 16, and
discussed throughout this section. When XC4000X special
features are discussed, they are clearly identied in the
text. Any feature not so identied is present in both
XC4000E and XC4000X devices.
IOB Input Signals
Two paths, labeled I1 and I2 in Figure 15 and Figure 16,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an
edge-triggered ip-op or a level-sensitive latch.
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input ip-op (rising edge
triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and
some combinations of latches and ip-ops can be imple-
mented in a single IOB, as described in the
XACT Libraries
Guide.
The XC4000E inputs can be globally congured for either
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
the bitstream generation software. There is a slight input
hysteresis of about 300mV. The XC4000E output levels are
also congurable; the two global adjustments of input
threshold and output level are independent.
Inputs on the XC4000XL are TTL compatible and 3.3V
CMOS compatible. Outputs on the XC4000XL are pulled to
the 3.3V positive supply.
The inputs of XC4000 Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000 Series device inputs are
shown in Table 8.
01
M
0
1
01
M
0
1
M
10
M
0
3
M
1
M
I
G1
G4
F2
F1
F3
COUT
G2
G3
F4
C INUP
C IN DOWN
X2000
TO
FUNCTION
GENERATORS
M
C OUT0
Figure 14: Detail of XC4000E Dedicated Carry Logic
Product Obsolete or Under Obsolescence
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XC4005XL-3TQ144M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4005XL-3VQ100C | 功能描述:IC FPGA C-TEMP 3.3V 3SP 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4005XL-3VQ100I | 功能描述:IC FPGA I-TEMP 3.3V 3SP 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應商設備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XC4005XL-3VQ100M | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4005XL-4PC84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays |
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