參數(shù)資料
      

      


      


      
型號：
XC4005E-3PQ160I

      

      
廠商：
Xilinx Inc

      

      
文件頁數(shù)：
41/68頁

      

      
文件大?。?/td>
0K

      

      
描述：
IC FPGA I-TEMP 5V 3-SPD 160-PQFP

      

      
產(chǎn)品變化通告：
Product Discontinuation 28/Jul/2010
      		

      

      
標(biāo)準(zhǔn)包裝：
24

      

      
系列：
XC4000E/X

      

      
LAB/CLB數(shù)：
196
      		

      

      
邏輯元件/單元數(shù)：
466
      		

      

      
RAM 位總計：
6272
      		

      

      
輸入/輸出數(shù)：
112
      		

      

      
門數(shù)：
5000
      		

      

      
電源電壓：
4.5 V ~ 5.5 V
      		

      

      
安裝類型：
表面貼裝
      		

      

      
工作溫度：
-40°C ~ 100°C
      		

      

      
封裝/外殼：
160-BQFP
      		

      

      
供應(yīng)商設(shè)備封裝：
160-PQFP（28x28）
      		

      

      

      

	
      
    
    

    
      
	
      R
      XC4000E and XC4000X Series Field Programmable Gate Arrays
      6-50
      May 14, 1999 (Version 1.6)
      used), and if RAM is present, the RAM content must be
      unchanged.
      Statistically, one error out of 2048 might go undetected.
      Conguration Sequence
      There are four major steps in the XC4000 Series power-up
      conguration sequence.
      Conguration Memory Clear
      Initialization
      Conguration
      Start-Up
      The full process is illustrated in Figure 46.
      Conguration Memory Clear
      When power is rst applied or is reapplied to an FPGA, an
      internal circuit forces initialization of the conguration logic.
      When Vcc reaches an operational level, and the circuit
      passes the write and read test of a sample pair of congu-
      ration bits, a time delay is started. This time delay is nomi-
      nally 16 ms, and up to 10% longer in the low-voltage
      devices. The delay is four times as long when in Master
      Modes (M0 Low), to allow ample time for all slaves to reach
      a stable Vcc. When all INIT pins are tied together, as rec-
      ommended, the longest delay takes precedence. There-
      fore, devices with different time delays can easily be mixed
      and matched in a daisy chain.
      This delay is applied only on power-up. It is not applied
      when re-conguring an FPGA by pulsing the PROGRAM
      pin
      0
      X2
      2 3456789 10 11 12 13 14
      1
      X15
      X16
      15
      SERIAL DATA IN
      1 0 1514 13 12 1110 9 8 7 65
      1
      CRC – CHECKSUM
      LAST DATA FRAME
      START
      BIT
      X1789
      Polynomial: X16 + X15 + X2 + 1
      Readback Data Stream
      Figure 45: Circuit for Generating CRC-16
      INIT
      High? if
      Master
      Sample
      Mode Lines
      Load One
      Configuration
      Data Frame
      Frame
      Error
      Pass
      Configuration
      Data to DOUT
      VCC
      >3.5 V
      No
      Yes
      No
      Yes
      Operational
      Start-Up
      Sequence
      No
      Yes
      ~1.3
      s per Frame
      Master Waits 50 to 250
      s
      Before Sampling Mode Lines
      Master CCLK
      Goes Active
      F
      Pull INIT Low
      and Stop
      X6076
      EXTEST*
      SAMPLE/PRELOAD
      BYPASS
      CONFIGURE*
      (* if PROGRAM = High)
      SAMPLE/PRELOAD
      BYPASS
      EXTEST
      SAMPLE PRELOAD
      BYPASS
      USER 1
      USER 2
      CONFIGURE
      READBACK
      If Boundary Scan
      is Selected
      Config-
      uration
      memory
      Full
      CCLK
      Count Equals
      Length
      Count
      Completely Clear
      Configuration Memory
      Once More
      LDC
      Output
      =
      L,
      HDC
      Output
      =
      H
      Boundary Scan
      Instructions
      Available:
      I/O
      Active
      Keep Clearing
      Configuration Memory
      Test M0 Generate
      One Time-Out Pulse
      of 16 or 64 ms
      PROGRAM
      = Low
      No
      Yes
      Figure 46: Power-up Conguration Sequence
      Product Obsolete or Under Obsolescence
      
    
      
    
    
      


      


      

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      相關(guān)代理商/技術(shù)參數(shù)
      		

      參數(shù)描述
      		

      
      

      
XC4005E-3PQ208C
功能描述:IC FPGA C-TEMP 5V 3-SPD 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4005E-3PQ208I
功能描述:IC FPGA I-TEMP 5V 3-SPD 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4005E-3TQ144C
功能描述:IC FPGA C-TEMP 5V 3-SPD 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4005E-3TQ144I
功能描述:IC FPGA I-TEMP 5V 3-SPD 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC4000E/X 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789

      

      
XC4005E-4CB164B
 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)

      

      
    
    
    
	
      	
    
    
     
     
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