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    參數(shù)資料
    型號: XC4005E-2PC84C
    廠商: Xilinx Inc
    文件頁數(shù): 4/68頁
    文件大小: 0K
    描述: IC FPGA C-TEMP 5V 2-SPD 84-PLCC
    產(chǎn)品變化通告: Product Discontinuation 28/Jul/2010
    標準包裝: 15
    系列: XC4000E/X
    LAB/CLB數(shù): 196
    邏輯元件/單元數(shù): 466
    RAM 位總計: 6272
    輸入/輸出數(shù): 61
    門數(shù): 5000
    電源電壓: 4.75 V ~ 5.25 V
    安裝類型: 表面貼裝
    工作溫度: 0°C ~ 85°C
    封裝/外殼: 84-LCC(J 形引線)
    供應商設(shè)備封裝: 84-PLCC
    R
    XC4000E and XC4000X Series Field Programmable Gate Arrays
    6-16
    May 14, 1999 (Version 1.6)
    Figure 8 shows the write timing for level-sensitive, sin-
    gle-port RAM.
    The relationships between CLB pins and RAM inputs and
    outputs for single-port level-sensitive mode are shown in
    Figure 9 and Figure 10 show block diagrams of a CLB con-
    gured as 16x2 and 32x1 level-sensitive, single-port RAM.
    Initializing RAM at Conguration
    Both RAM and ROM implementations of the XC4000
    Series devices are initialized during conguration. The ini-
    tial contents are dened via an INIT attribute or property
    attached to the RAM or ROM symbol, as described in the
    schematic library guide. If not dened, all RAM contents
    are initialized to all zeros, by default.
    RAM initialization occurs only during conguration. The
    RAM content is not affected by Global Set/Reset.
    Table 7: Single-Port Level-Sensitive RAM Signals
    G'
    G1 G4
    F1 F4
    WRITE
    DECODER
    1 of 16
    DIN
    16-LATCH
    ARRAY
    X6748
    4
    MUX
    F'
    WRITE
    DECODER
    1 of 16
    DIN
    16-LATCH
    ARRAY
    READ
    ADDRESS
    READ
    ADDRESS
    WRITE PULSE
    LATCH
    ENABLE
    LATCH
    ENABLE
    K
    (CLOCK)
    WRITE PULSE
    MUX
    4
    C1 C4
    4
    WE
    D1
    D0
    EC
    Figure 7: 16x1 Edge-Triggered Dual-Port RAM
    RAM Signal
    CLB Pin
    Function
    D
    D0 or D1
    Data In
    A[3:0]
    F1-F4 or G1-G4
    Address
    WE
    Write Enable
    O
    F’ or G’
    Data Out
    WC
    T
    ADDRESS
    WRITE ENABLE
    DATA IN
    AS
    T
    WP
    T
    DS
    T
    DH
    T
    REQUIRED
    AH
    T
    X6462
    Figure 8: Level-Sensitive RAM Write Timing
    Product Obsolete or Under Obsolescence
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